Device operation M24C64-DF, M24C64-W, M24C64-R, M24C64-F
14/44 Doc ID 16891 Rev 26
4.5 Memory addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in Ta bl e 3 (on Serial Data (SDA), most significant bit first).
The device select code consists of a 4-bit device type identifier, and a 3-bit Chip Enable
“Address” (E2, E1, E0). To address the memory array, the 4-bit device type identifier is
1010b. Up to eight memory devices can be connected on a single I
2
C bus
(a)
. Each one is
given a unique 3-bit code on the Chip Enable (E2, E1, E0) inputs. When the device select
code is received, the device only responds if the Chip Enable Address is the same as the
value on the Chip Enable (E2, E1, E0) inputs.
The 8
th
bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the device select code, the corresponding device gives an
acknowledgment on Serial Data (SDA) during the 9
th
bit time. If the device does not match
the device select code, it deselects itself from the bus, and goes into Standby mode.
a. Only one M24C64 in WLCSP package can be connected on the I²C bus (see Figure 4).
Table 5. Operating modes
Mode RW bit WC
(1)
1. X = V
IH
or V
IL
.
Bytes Initial sequence
Current Address
Read
1 X 1 Start, device select, RW
= 1
Random Address
Read
0X
1
Start, device select, RW = 0, Address
1 X reStart, device select, RW
= 1
Sequential Read 1 X ≥ 1
Similar to Current or Random Address
Read
Byte Write 0 V
IL
1 Start, device select, RW = 0
Page Write 0 V
IL
≤ 32 Start, device select, RW = 0
