M24C64-DF, M24C64-W, M24C64-R, M24C64-F DC and AC parameters
Doc ID 16891 Rev 26 31/44
Table 18. 1 MHz AC characteristics
(1)
1. Only M24C64 and M24C64-D devices identified by the process letter K are qualified at 1 MHz.
Symbol Alt. Parameter
(2)
2. Test conditions (in addition to those in Table 7, Table 8, Ta ble 9 and Table 10).
Min. Max. Unit
f
C
f
SCL
Clock frequency 0 1 MHz
t
CHCL
t
HIGH
Clock pulse width high 260 - ns
t
CLCH
t
LOW
Clock pulse width low 400 - ns
t
XH1XH2
t
R
Input signal rise time
(3)
3. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
f
C
< 400 kHz, or less than 120 ns when f
C
<1MHz.
(3)
ns
t
XL1XL2
t
F
Input signal fall time
(3) (3)
ns
t
QL1QL2
(8)
t
F
SDA (out) fall time - 120 ns
t
DXCX
t
SU:DAT
Data in setup time 50 - ns
t
CLDX
t
HD:DAT
Data in hold time 0 - ns
t
CLQX
t
DH
Data out hold time 100 - ns
t
CLQV
(4)(5)
4. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
5. t
CLQV
is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 V
CC
or
0.7 V
CC
, assuming that the Rbus × Cbus time constant is within the values specified in Figure 6.
t
AA
Clock low to next data valid (access time) 450 ns
t
CHDL
t
SU:STA
Start condition setup time 250 - ns
t
DLCL
t
HD:STA
Start condition hold time 250 - ns
t
CHDH
t
SU:STO
Stop condition setup time 250 - ns
t
DHDL
t
BUF
Time between Stop condition and next Start
condition
500 - ns
t
WLDL
(6)(8)
6. WC=0 set up time condition to enable the execution of a WRITE command.
t
SU:WC
WC set up time (before the Start condition) 0 - µs
t
DHWH
(7)(8)
7. WC=0 hold time condition to enable the execution of a WRITE command.
t
HD:WC
WC hold time (after the Stop condition) 1 - µs
t
W
t
WR
Write time - 5 ms
t
NS
(8)
8. Characterized only, not tested in production.
Pulse width ignored (input filter on SCL and
SDA)
-80ns
