AD1953
–25–
Soft Shutdown Mechanism
When writing large amounts of data to the program or parameter
RAM, the processor core should be halted to prevent unpleasant
noises from appearing at the audio output. Figure 18 shows a
graphical representation of this mechanism’s volume envelope.
Points A to D are referenced in the following description. Bit
<10> in serial Control Register 0 (processor shutdown bit) will
shut down the processor core. When the processor shutdown bit
is asserted (A), an automatic volume ramp-down sequence (B)
lasting from 10 ms to 20 ms will occur, followed by a shutdown
of the core. This method of shutting down the core prevents pops
or clicks from occurring. After the shutdown is complete, Bit
<1> in Control Register 1 will be set. The user can either poll
for this bit to be set, or just wait for a period longer than 20 ms.
Once the core is shut down (C), the parameter or program RAMs
may be written or read freely. To ease the transfer of large blocks
of sequential data, a block transfer mode is supported where a
starting address followed by a stream of data is sent to the memory.
The address into the memory will be automatically incremented
for each new write. This mode is documented in the SPI Data
Format section of this data sheet.
Once the data has been written, the shutdown bit can be cleared
(D). The processor then will initiate a volume ramp-up sequence
lasting 10 ms to 20 ms. Again, this reduces the chance that any
pop or click noise will occur.
Note that this shutdown sequence assumes the part is set to the
fast volume ramp speed (Control Register 2, Bit <9>). If the
slow ramp speed is set, the volume may not reach zero before
the part enters shutdown, and a click or pop may be heard.
Safeload Mechanism
Many applications require real-time control of filter characteristics,
such as bass/treble controls and parametric or graphic equaliza-
tion. To prevent instability from occurring, all of the parameters
of a particular biquad filter must be updated at the same time;
otherwise, the filter could execute for one or two audio frames
with a mixture of old and new coefficients. This mix of old and
new could cause temporary instability, leading to transients that
could take a long time to decay.
The method used in the AD1953 to eliminate this problem is to
load a set of five registers in the SPI port with the desired param-
eter RAM address and data. Five registers are used because each
biquad filter has five coefficients. Once these registers are loaded,
the initiate safe transfer bit in SPI Control Register 1 is set.
Once this bit is set, the processor waits for a period of time in
the program sequence when the parameter RAM is not being
accessed for at least five consecutive instruction cycles. When
the program counter reaches this point, the parameter RAM is
written with five new data values at addresses corresponding to
those entered in the safeload registers. When the operation is
complete, Bit 0 of Control Register 1 is set. This bit may be
polled by the external microprocessor until a 1 is read. This bit
will be reset on a read operation. The polling operation is not
required; the safeload mechanism guarantees that the transfer
will be complete within one audio frame.
The safeload logic automatically sends only those safeload regis-
ters that have been written to since the last safeload operation.
For example, if only two parameters are to be sent, it is only
necessary to write to two of the five safeload registers. When the
request safe transfer bit is asserted, only those two registers will
be sent; the other three registers are not sent, and can still hold
old or invalid data.
The safeload mechanism is not limited to uploading biquad
coefficients; any set of five values in the parameter RAM may be
updated in the same way. This allows real-time adjustment of
the compressor/limiter, delay, or stereo spreading blocks.
Summary of RAM Modes
Table VII shows the sizes and available modes of the parameter
RAM and the program RAM.
ADC
B
Figure 18. Recommended Sequences for Complete Parameter or Program RAM Upload Using Shutdown Mechanism
Table VII. Read/Write Modes
Memory Size SPI Address Range Read Write Burst Mode Available Write Modes
Parameter RAM 256
×
22 0–255 Yes Yes Yes Direct Write, Write after core
shutdown, safeload write
Program RAM 512
×
35 512–1023 Yes Yes Yes Direct Write, Write after core
shutdown
REV. A
