42681fc
LTC4268-1
19
consume a lot of power, it is important to delay activation
of the DC/DC converter with the power good signal. If
the converter is not disabled during the current-limited
turn-on sequence, the DC/DC converter will rob current
intended for charging up the load capacitor and create a
slow rising input, possibly causing the LTC4268-1 to go
into thermal shutdown.
The active high PWRGD pin features an internal,
open-collector output referenced to V
NEG
. During inrush,
the active high PWRGD pin becomes valid when C1 reaches
–4V and pulls low until the load capacitor is fully charged.
At that point, PWRGD becomes high impedance, indicating
the switching regulator may begin running. The active
high PWRGD pin interfaces directly to the UVLO pin of
the LTC4268-1 with the aid of an external pull-up resistor
to Vcc. The PWRGD pin includes an internal 14V clamp to
V
NEG
. During a power supply ramp down event, PWRGD
becomes low impedance when V
PORT
drops below the 30V
PD UVLO turn-off threshold, then goes high impedance
when the V
PORT
voltages fall to within the detection voltage
range. Figure 11 shows a typical connection scheme for
the active high PWRGD
pin.
The
LTC4268-1 also includes an active low PWRGD pin
for system level use. PWRGD is referenced to the V
PORTN
pin and when active will be near the V
PORTN
potential. The
negative rail (GND) of the internal switching regulator will
typically be referenced to V
NEG
and care must be taken to
ensure that the difference in potential of the PWRGD pin
does not cause a problem for the switcher.
THERMAL PROTECTION
The LTC4268-1 includes thermal overload protection in
order to provide full device functionality in a miniature
package while maintaining safe operating temperatures.
At turn-on, before load capacitor C1 has charged up, the
instantaneous power dissipated by the LTC4268-1 can be
as high as 20W. As the load capacitor charges, the power
dissipation in the LTC4268-1 will decrease until it reaches
a steady-state value dependent on the DC load current.
The LTC4268-1 can also experience device heating after
turn-on if the PD experiences a fast input voltage rise. For
example, if the PD input voltage steps from –37V to –57V,
the instantaneous power dissipated by the LTC4268-1 can
be as high as 16W. The LTC4268-1 protects itself from
damage by monitoring die
temperature. If
the die exceeds
the overtemperature trip point, the power MOSFET and
classification transistors are disabled until the part cools
down. Once the die cools below the overtemperature trip
point, all functions are enabled automatically. During
classification, excessive heating of the LTC4268-1 can
occur if the PSE violates the 75ms probing time limit.
In addition, the IEEE 802.3af specification requires a PD
to withstand application of any voltage from 0V to 57V
indefinitely. To protect the LTC4268-1 in these situations,
the thermal protection circuitry disables the classification
circuit and the input current if the die temperature exceeds
the overtemperature trip point. When the die cools down,
classification and input current are enabled.
Once the LTC4268-1 has charged up the load capacitor and
the PD is powered and running, there will be some residual
heating due to the DC load current of the PD flowing through
the internal MOSFET. In some high current applications,
the LTC4268-1 power dissipation may be significant. The
LTC4268-1 uses a thermally enhanced DFN package that
includes an exposed pad which should be soldered to the
GND plane for heat sinking on the printed circuit board.
MAXIMUM AMBIENT TEMPERATURE
The LTC4268-1 I
LIM_EN
pin allows the PD designer to
disable the normal operating current limit. With the normal
current limit disabled, it is possible to pass currents
as high as 1.4A through the LTC4268-1. In this mode,
significant package heating may occur. Depending on
the current, voltage, ambient temperature, and waveform
characteristics, the LTC4268-1 may shut down. To avoid
nuisance trips of the thermal shutdown, it may be necessary
to limit the maximum ambient temperature. Limiting the
die temperature to 125°C will keep the LTC4268-1 from
hitting thermal shutdown. For DC loads the maximum
ambient temperature can be calculated as:
T
MAX
= 125 – θ
JA
PWR (°C)
where T
MAX
is the maximum ambient operating tempera-
ture, θ
JA
is the junction-to-ambient thermal resistance
(49°C/W), and PWR is the power dissipation for the
LTC4268-1 in Watts (I
PD
2
R
ON
).
applicaTions inForMaTion
LTC4268-1
20
42681fc
EXTERNAL INTERFACE AND COMPONENT SELECTION
Transformer
Nodes on an Ethernet network commonly interface to
the outside world via an isolation transformer (Figure
9). For powered devices, the isolation transformer must
include a center tap on the media (cable) side. Proper
termination is required around the transformer to pro-
vide correct impedance matching and to avoid radiated
and conducted emissions. For high power applications
beyond IEEE 802.3af limits, the increased current levels
increase the current imbalance in the magnetics. This
imbalance reduces the perceived inductance and can
interfere with data transmission. Transformers specifi-
cally designed for high current applications are required.
Transformer vendors such as Bel Fuse, Coilcraft, Halo,
Pulse, and Tyco (Table 4) can provide assistance with
selection of an appropriate isolation transformer and
proper termination methods. These vendors have trans-
formers specifically designed for use in high power PD
applications.
Table 4. Power over Ethernet Transformer Vendors
V
PORT
MODE OF OPERATION
Bel Fuse Inc. 206 Van Vorst Street
Jersey City, NJ 07302
Tel: 201-432-0463
www.belfuse.com
Coilcraft Inc. 1102 Silver Lake Road
Gary, IL 60013
Tel: 847-639-6400
www.coilcraft.com
Halo Electronics 1861 Landings Drive
Mountain View, CA 94043
Tel: 650-903-3800
www.haloelectronics.com
Pulse Engineering 12220 World Trade Drive
San Diego, CA 92128
Tel: 858-674-8100
www.pulseeng.com
Tyco Electronics 308 Constitution Drive
Menlo Park, CA 94025-1164
Tel: 800-227-7040
www.circuitprotection.com
IEEE 802.3af allows power wiring in either of two configu-
rations on the TX/RX wires, and power can be applied to
the PD via the spare wire pair in the RJ45 connector. The
applicaTions inForMaTion
16
14
15
1
3
2
RX
6
RX
+
3
TX
2
TX
+
RJ45
T1
PULSE H2019
42681 F09
1
7
8
5
4
11
9
10
6
8
4 5
8
7
D3
SMAJ58A
TVS
BR1
HD01
10Ω
BR2
HD01
TO PHY
V
PORTP
V
OUT
LTC4268-1
C1
V
PORTN
V
NEG
SPARE
SPARE
+
C14
0.1µF
100V
Figure 9. PD Front-End Isolation Transformer, Diode Bridges, Capacitors and TVS
42681fc
LTC4268-1
21
PD is required to accept power in either polarity on both
the data and spare inputs; therefore it is common to install
diode bridges on both inputs in order to accommodate the
different wiring configurations. Figure 9 demonstrates an
implementation of the diode bridges to minimize heating.
The IEEE 802.3af specification also mandates that the
leakage back through the unused bridge be less than 28µA
when the PD is powered with 57V.
The LTC4268-1 has several different modes of operation
based on the voltage present between the V
PORTN
and
V
PORTP
pins. The forward voltage drop of the input diodes
in a PD design subtracts from the input voltage and will
affect the transition point between modes.
The input diode bridge of a PD can consume over 4% of
the available power in some applications. Schottky diodes
can be used in order to reduce power loss. The LTC4268-1
is designed to work with both standard and Schottky
diode bridges while maintaining proper threshold points
for IEEE 802.3af compliance.
Input Capacitor
The IEEE 802.3af/at standard includes an impedance
requirement in order to implement the AC disconnect
function. A 0.1µF capacitor (C14 in Figure 9) is used to
meet the AC impedance requirement.
Input
Series Resistance
Li
near Technology has seen the customer community cable
discharge requirements increase by nearly 500,000 times
the original test levels. The PD must survive and operate
reliably not only when an initially charged cable connects
and dissipates the energy through the PD front end, but
also when the electrical power system grounds are subject
to very high energy events (e.g., lightning strikes).
In these high energy events, adding 10Ω series resistance
into the V
PORTP
pin greatly improves the robustness of
the LTC4268-1 based PD (see Figure 9). The TVS limits
the voltage across the port while the 10Ω and 0.1µF ca-
pacitance reduces the edge rate the LT4268-1 encounters
across its pin. The added 10Ω series resistance does not
operationally affect the LTC4268-1 PD Interface, nor does
it affect its compliance with the IEEE 802.3 standard.
Transient Voltage Suppressor
The LTC4268-1 specifies and absolute maximum volt-
age of 100V and is designed to tolerate brief overvoltage
events. However, the pins that interface to the outside
world can routinely see excessive peak voltages. To pro-
tect the LTC4268-1, install a transient voltage suppressor
(D3) between the input diode bridge and the LTC4268-1,
as shown in Figure 9. An SMAJ58A is recommended for
typical
PD applications. However, an SMBJ58A may be
preferred in applications where the PD front end must
absorb higher energy discharge events.
Auxiliary Power Source
In some applications, it may be necessary to power the
PD from an auxiliary power source such as a wall adapter.
The auxiliary power can be injected into the PD at several
locations and various trade-offs exist. Figure 10 demon-
strates four methods of connecting external power to a PD.
Option 1 in Figure 10 inserts power before the LTC4268-1
interface controller. In this configuration, it is necessary
for the wall adapter to exceed the LTC4268-1 UVLO turn-
on requirement. This option provides input current limit
for the adapter, provides a valid power good signal and
simplifies power priority issues. As long as the adapter
applies power to the PD before the PSE, it will take priority
and the PSE will not power up the PD because the external
power source will corrupt the 25k signature. If the PSE
is already powering the PD, the adapter power will be in
parallel with the PSE. In this case, priority will be given to
the higher supply voltage. If the adapter voltage is higher,
the PSE may
remove the port voltage since no current will
be
drawn from the PSE. On the other hand, if the adapter
voltage is lower, the PSE will continue to supply power to
the PD and the adapter will not be used. Proper operation
will occur in either scenario.
Option 2 applies power directly to the DC/DC converter.
In this configuration the adapter voltage does not need
to exceed the LTC4268-1 turn-on UVLO requirement and
can be selected based solely on the PD load requirements.
It is necessary to include diode D9 to prevent the adapter
from applying power to the LTC4268-1. Power priority
issues require more intervention. If the adapter voltage
is below the PSE voltage, then the priority will be given
applicaTions inForMaTion

LTC4268IDKD-1#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Power Switch ICs - POE / LAN EEE 802.3af High Power PD with Synchronous NoOpto Flyback Controller
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union