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LTC4268IDKD-1#TRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P46
LTC4268-1
28
42681fc
applicaTions inForMaTion
lowpass filtered by the internal 50k resistor R
CMPF
and
the external capacitor on C
CMP
. This voltage is impressed
across the external R
CMP
resistor by op amp A1 and
transistor Q3 producing a current at the collector of Q3 that
is subtracted from the FB node. This effectively increases
the voltage required at the top of the R1/R2 feedback
divider to achieve equilibrium.
The average primary side switch current increases to
maintain output voltage regulation as output loading
increases. The increase in average current increases R
CMP
resistor current which affects a corresponding increase
in sensed output voltage, compensating for the IR drops.
Assuming relatively fixed power supply efficiency, Eff,
power balance gives:
P
OUT
= Eff • P
IN
V
OUT
• I
OUT
= Eff • V
IN
• I
IN
Average primary side current is expressed in terms of
output current as follow:
I
IN
=K1• I
OUT
where:
K1=
V
OUT
V
IN
• Eff
So the effective change in V
OUT
target is:
DV
OUT
=K1•
R
SENSE
R
CMP
• R1• N
SF
thus:
DV
OUT
DI
OUT
=K1•
R
SENSE
R
CMP
• R1• N
SF
where:
K1 = dimensionless variable related to V
IN
,
V
OUT
and efficiency as explained above
R
SENSE
= external sense resistor
Nominal output impedance cancellation is obtained by
equating this expression with R
S(OUT)
:
K1•
R
SENSE
R
CMP
• R1• N
SF
=
ESR +R
DS(ON)
1−DC
Solving for R
CMP
gives:
R
CMP
=K1•
R
SENSE
• 1−DC
( )
ESR +R
DS(ON)
• R1• N
SF
The practical aspects of applying this equation to determine
an appropriate value for the R
CMP
resistor are found in the
Applications Information.
Transformer Design
Transformer design/specification is the most critical part of
a successful application of the LTC4268-1. The following
sections provide basic information about designing the
transformer and potential trade-offs. If you need help, the
LT C Applications group is available to assist in the choice
and/or design of the transformer.
Turns Ratios
The design of the transformer starts with determining
duty cycle (DC). DC impacts the current and voltage stress
on the power switches, input and output capacitor RMS
currents and transformer utilization (size vs power). The
ideal turns ratio is:
N
DEAL
=
V
OUT
V
IN
•
1−DC
DC
Avoid extreme duty cycles as they, in general, increase
current stresses. A reasonable target for duty cycle is 50%
at nominal input voltage.
For instance, if we wanted a 48V to 5V converter at 50%
DC then:
N
DEAL
=
5
48
•
1− 0.5
0.5
=
1
9.6
42681fc
LTC4268-1
29
applicaTions inForMaTion
In general, better performance is obtained with a lower
turns ratio. A DC of 45.5% yields a 1:8 ratio. Note the
use of the external feedback resistive divider ratio to set
output voltage provides the user additional freedom in
selecting a suitable transformer turns ratio. Turns ratios
that are the simple ratios of small integers; e.g., 1:1, 2:1,
3:2 help facilitate transformer construction and improve
performance. When building a supply with multiple
outputs derived through a multiple winding transformer,
lower duty cycle can improve cross regulation by keeping
the synchronous rectifier on longer, and thus, keep
secondary windings coupled longer. For a multiple output
transformer, the turns ratio between output windings is
critical and affects the accuracy of the voltages. The ratio
between two output voltages is set with the formula V
OUT2
= V
OUT1
• N21 where N21 is the turns ratio between the
two windings. Also keep the secondary MOSFET R
DS(ON)
small to improve cross regulation. The feedback winding
usually provides both the feedback voltage and power for
the LTC4268-1. Set the turns ratio between the output and
feedback winding to provide a rectified voltage that under
worst-case conditions is greater than the 11V maximum
V
CC
turn-off voltage.
N
SF
>
V
OUT
11+ V
F
where:
V
F
=Diode Forward Voltage
For our example: N
SF
>
5
11+ 0.7
=
1
2.34
We will choose
1
3
Leakage Inductance
Transformer leakage inductance (on either the primary or
secondary) causes a spike after the primary side switch
turn-off. This is increasingly prominent at higher load
currents, where more stored energy is dissipated. Higher
flyback voltage may break down the MOSFET switch if it
has too low a BV
DSS
rating. One solution to reducing this
spike is to use a snubber circuit to suppress the voltage
excursion. However, suppressing the voltage extends the
flyback pulse width. If the flyback pulse extends beyond
the enable delay time, output voltage regulation is affected.
The feedback system has a deliberately limited input range,
roughly ±50mV referred to the FB node. This rejects higher
voltage leakage spikes because once a leakage spike is
several volts in amplitude; a further increase in amplitude
has little effect on the feedback system. Therefore, it is
advisable to arrange the snubber circuit to clamp at as
high a voltage as possible, observing MOSFET breakdown,
such that leakage spike duration is as short as possible.
Application Note 19 provides a good reference on snubber
design.
As a rough guide, leakage inductance of several percent
(of mutual inductance) or less may require a snubber, but
exhibit little to no
regulation error due to leakage spike
behavior.
Inductances from several percent up to perhaps
ten percent cause increasing regulation error.
Avoid double digit percentage leakage inductances. There
is a potential for abrupt loss of control at high load current.
This curious condition potentially occurs when the leakage
spike becomes such a large portion of the flyback waveform
that the processing circuitry is fooled into thinking that
the leakage spike itself is the real flyback signal! It then
reverts to a potentially stable state whereby the top of the
leakage spike is the control point, and the trailing edge of
the leakage spike triggers the collapse detect circuitry. This
typically reduces the output voltage abruptly to a fraction,
roughly one-third to two-thirds of its correct value. Once
load current is reduced sufficiently, the system snaps
back to normal operation. When using transformers with
considerable leakage inductance, exercise this worst-case
check for potential bistability:
1. Operate the prototype supply at maximum expected
load current.
2. Temporarily short-circuit the output.
3. Observe that normal operation is restored.
If the output voltage is found to hang up at an abnormally
low value, the system has a problem. This is usually evident
by simultaneously
viewing the primary side MOSFET drain
voltage to observe firsthand the leakage spike behavior.
A final note—the susceptibility of the system to bistable
behavior is somewhat a function of the load current/
voltage characteristics. A load with resistive—i.e., I = V/R
LTC4268-1
30
42681fc
applicaTions inForMaTion
behavior—is the most apt to be bistable. Capacitive loads
that exhibit I = V
2
/R behavior are less susceptible.
Secondary Leakage Inductance
Leakage inductance on the secondary forms an inductive
divider on the transformer secondary, reducing the size
of the flyback pulse. This increases the output voltage
target by a similar percentage. Note that unlike leakage
spike behavior; this phenomenon is independent of load.
Since the secondary leakage inductance is a constant
percentage of mutual inductance (within manufacturing
variations), the solution is to adjust the feedback resistive
divider ratio to compensate.
Winding Resistance Effects
Primary or secondary winding resistance acts to reduce
overall efficiency (P
OUT
/P
IN
). Secondary winding resistance
increases effective output impedance, degrading load
regulation. Load compensation can mitigate this to some
extent but a good design keeps parasitic resistances low.
Bifilar Winding
A bifilar or similar winding is a good way to minimize
troublesome leakage inductances. Bifilar windings also
improve coupling coefficients and thus improve cross
regulation in multiple winding transformers. However,
tight coupling usually increases primary-to-secondary
capacitance and limits the primary-to-secondary
breakdown voltage, so it isn’t always practical.
Primary Inductance
The transformer primary inductance, L
P
, is selected
based on the peak-to-peak ripple current ratio (X) in the
transformer relative to its maximum value.
As
a general rule, keep X in the range of 20% to 40%
(i.e., X = 0.2 to 0.4). Higher values of ripple will increase
conduction losses, while lower values will require larger
cores.
Ripple current and percentage ripple is largest at minimum
duty cycle; in other words, at the highest input voltage.
L
P
is calculated from:
L
P
=
V
IN(MAX)
• DC
MIN
( )
2
f
OSC
• X
MAX
• P
IN
=
V
IN(MAX)
• DC
MIN
( )
2
• Eff
f
OSC
• X
MAX
• P
OUT
where:
f
OSC
is the oscillator frequency
DC
MIN
is the DC at maximum input voltage
X
MAX
is ripple current ratio at maximum input voltage
Using common high power PoE values a 48V (41V < V
IN
< 57V) to 5V/5.3A Converter with 90% efficiency, P
OUT
=
26.5W and P
IN
= 29.5W Using X = 0.4 N = 1/8 and f
OSC
= 200kHz:
DC
MIN
=
1
1+
N • V
IN(MAX)
V
OUT
=
1
1+
1
8
•
57
5
= 41.2%
L
P
=
57V • 0.412
( )
2
200kHz • 0.4 • 26.5W
= 260µH
Optimization might show that a more efficient solution
is obtained at higher peak current but lower inductance
and the associated winding series resistance. A simple
spreadsheet program is useful for looking at trade-offs.
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LTC4268IDKD-1#TRPBF

Mfr. #:
Buy LTC4268IDKD-1#TRPBF
Manufacturer:
Analog Devices Inc.
Description:
Power Switch ICs - POE / LAN EEE 802.3af High Power PD with Synchronous NoOpto Flyback Controller
Lifecycle:
New from this manufacturer.
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