42681fc
LTC4268-1
41
Most capacitor ripple current ratings are based on 2000
hour life. This makes it advisable to derate the capacitor
or to choose a capacitor rated at a higher temperature
than required.
One way to reduce cost and improve output ripple is to use
a simple LC filter. Figure 20 shows an example of the filter.
The design of the filter is beyond the scope of this data
sheet. However, as a starting point, use these general
guidelines. Start with a C
OUT
1/4 the size of the nonfilter
solution. Make C1 1/4 of C
OUT
to make the second filter
pole independent of C
OUT
. C1 may be best implemented
with multiple ceramic capacitors. Make L1 smaller than
the output inductance of the transformer. In general, a
0.1µH filter inductor is sufficient. Add a small ceramic
capacitor (C
OUT2
) for high frequency noise on V
OUT
. For
those interested in more details refer to “Second-Stage
LC Filter Design,” Ridley, Switching Power Magazine, July
2000 p8-10.
Circuit simulation is a way to optimize output capacitance
and filters, just make sure to include the component
parasitic. LT C SwitcherCAD
®
is a terrific free circuit
simulation tool that is available at www.linear.com. Final
optimization of output ripple
must be done on a dedicated
PC
board. Parasitic inductance due to poor layout can
significantly impact ripple. Refer to the PC Board Layout
section for more details.
ISOLATION
The 802.3 standard requires Ethernet ports to be electrically
isolated from all other conductors that are user accessible.
This includes the metal chassis, other connectors and
any auxiliary power connection. For PDs, there are two
common methods to meet the isolation requirement. If
there will be any user accessible connection to the PD,
then an isolated DC/DC converter is necessary to meet
the isolation requirements. If user connections can be
avoided, then it is possible to meet the safety requirement
by completely enclosing the PD in an insulated housing.
In all PD applications, there should be no user accessible
electrical connections to the LTC4268-1 or support circuitry
other than the RJ-45 port.
LAYOUT CONSIDERATIONS FOR THE LTC4268-1
The LTC4268-1’s PD front end is relatively immune to
layout problems. Place C14 (Figure 9) as close as physically
possible to the LTC4268-1. Place the series 10Ω resistor
close to C14. Excessive parasitic capacitance on the R
CLASS
pin should be avoided. Include a PCB heat sink to which
the exposed pad on the
bottom of the package can be
soldered.
This heat sink should be electrically connected
to GND. For optimum thermal performance, make the
heat sink as large as possible. Voltages in a PD can be
as large as –57V for PoE applications, so high voltage
layout techniques should be employed. The SHDN pin
should be separated from other high voltage pins, like
V
PORTP
, V
OUT
, to avoid the possibility of leakage shutting
down the LTC4268-1. If not used, tie SHDN to V
PORTN
.
The load capacitor connected between V
PORTP
and V
OUT
of the LTC4268-1 can store significant energy when fully
charged. The design of a PD must ensure that this energy
is not inadvertently dissipated in the LTC4268-1. The
polarity-protection diodes prevent an accidental short
on the cable from causing damage. However if, V
PORTN
is shorted to V
PORTP
inside the PD while capacitor C1
is charged, current will flow through the parasitic body
diode of the internal MOSFET and may cause permanent
damage to the LTC4268-1.
R
LOAD
C
OUT2
1µF
V
OUT
C
OUT
470µF
C1
47µF
×3
FROM
SECONDARY
WINDING
L1
0.1µH
42681 F20
++
Figure 20. LC Filter
applicaTions inForMaTion
