42681fc
LTC4268-1
27
side MOSFET drain node but, more importantly, is due
to transformer leakage inductance. The latter causes a
voltage spike on the primary side, not directly related to
output voltage. Some time is also required for internal
settling of the feedback amplifier circuitry. In order to
maintain immunity to these phenomena, a fixed delay is
introduced between the switch turn-off command and the
enabling of the feedback amplifier. This is termed “enable
delay.” In certain cases where the leakage spike is not
sufficiently settled by the end of the enable delay period,
regulation error may result. See Applications Information
for further details.
Collapse Detect
Once the feedback amplifier is enabled, some mechanism
is then required to disable it. This is accomplished by a
collapse detect comparator, which compares the flyback
voltage (FB) to a fixed reference, nominally 80% of V
FB
.
When the flyback waveform drops below this level, the
feedback amplifier is disabled.
Minimum Enable Time
The feedback amplifier, once enabled, stays on for a fixed
minimum time period termed “minimum enable time.”
This prevents lockup, especially when the output voltage
is abnormally low; e.g., during start-up. The minimum
enable time period ensures that the V
CMP
node is able to
“pump up” and increase the current mode trip point to
the level where the collapse detect system exhibits proper
operation. This time is set internally.
Effects of Variable Enable Period
The feedback amplifier is enabled during only a portion of
the cycle time. This can vary from the fixed minimum enable
time described to a maximum of roughly the “off” switch
time minus the enable delay time. Certain parameters of
feedback amp behavior are directly affected by the variable
enable period. These include effective transconductance
and V
CMP
node slew rate.
Load Compensation Theory
The LTC4268-1 uses the flyback pulse to obtain
information about the isolated output voltage. An error
source is caused by transformer secondary current flow
applicaTions inForMaTion
through the synchronous MOSFET R
DS(ON)
and real life
nonzero impedances of the transformer secondary and
output capacitor. This was represented previously by
the expression “I
SEC
• (ESR + R
DS(ON)
).” However, it is
generally more useful to convert this expression to effective
output impedance. Because the secondary current only
flows during the off portion of the duty cycle (DC), the
effective output impedance equals the lumped secondary
impedance divided by off time DC.
Since the off time duty
cycle is equal to 1 – DC then:
R
S(OUT)
=
ESR +R
DS(ON)
1
DC
where:
R
S(OUT)
= effective supply output impedance
DC = duty cycle
R
DS(ON)
and ESR are as defined previously
This impedance error may be judged acceptable in less
critical applications, or if the output load current remains
relatively constant. In these cases the external FB resistive
divider is adjusted to compensate for nominal expected
error. In more demanding applications, output impedance
error is minimized by the use of the load compensation
function. Figure 14 shows the block diagram of the load
compensation function. Switch current is converted to
a voltage by the external sense resistor, averaged and
T1
•
•
•
MP
R
CMPF
50k
V
PORTP
V
FLBK
R2
LOAD
COMP I
R1
FB
V
FB
Q1 Q2
R
CMP
C
CMP
R
SENSE
SENSE
+
42681 F13
Q3
–
+
A1
16
22 21
20
Figure 14. Load Compensation Diagram
