LTC4268-1
22
42681fc
applicaTions inForMaTion
RX
6
RX
+
3
TX
2
TX
+
RJ45
T1
1
7
8
5
4
SPARE
+
SPARE
+
ISOLATED
WALL
TRANSFORMER
TO PHY
V
PORTP
OPTION 1: AUXILIARY POWER INSERTED BEFORE LTC4268-1
OPTION 2: AUXILIARY POWER INSERTED AFTER LTC4268-1 WITH SIGNATURE DISABLED
V
PORTN
V
NEG
V
WW
V
WW
V
WW
D8
S1B
D3
SMAJ58A
TVS
C1
• 42V ≤ V
WW
≤ 57V
• NO POWER PRIORITY ISSUES
• LTC4268-1 CURRENT LIMITS FOR BOTH PoE AND V
WW
• 42V ≤ V
WW
≤ 57V
• NO POWER PRIORITY ISSUES
• NO LTC4268-1 CURRENT LIMITS FOR V
WW
• V
WW
ANY VOLTAGE BASED ON PD LOAD
• REQUIRES EXTRA DIODE
• SEE APPS REGARDING POWER PRIORITY
C14
0.1µF
100V
RX
6
RX
+
3
TX
2
TX
+
RJ45
T1
1
7
8
5
4
SPARE
+
SPARE
+
ISOLATED
WALL
TRANSFORMER
TO PHY
V
PORTP
LTC4268-1
LTC4268-1
BR2
~
~
+
BR1
~
~
+
BR1
~
~
+
V
PORTN
SHDN
BSS63
4.7k
100k
V
NEG
D10
S1B
D3
SMAJ58A
TVS
C1
D9
S1B
OPTION 3: AUXILIARY POWER APPLIED TO LTC4268-1 AND PD LOAD
RX
6
RX
+
3
TX
2
TX
+
RJ45
T1
1
7
8
5
4
SPARE
+
SPARE
+
ISOLATED
WALL
TRANSFORMER
TO PHY
V
PORTP
LTC4268-1
V
PORTN
V
NEG
D10
S1B
D3
SMAJ58A
TVS
C1
C14
0.1µF
100V
C14
0.1µF
100V
BR2
~
~
+
BR1
~
~
+
OPTION 4: AUXILIARY POWER APPLIED TO ISOLATED LOAD
BR2
~
~
+
V
WW
• V
WW
ANY VOLTAGE BASED ON PD LOAD
• SEE APPS REGARDING POWER PRIORITY
• BEST ISOLATION
RX
6
RX
+
3
TX
2
TX
+
RJ45
T1
1
7
8
5
4
SPARE
+
SPARE
+
ISOLATED
WALL
TRANSFORMER
TO PHY
V
PORTP
PG
GND
LTC4268-1
BR1
~
~
+
V
PORTN
SHDN
V
NEG
D3
SMAJ58A
TVS
C1
DRIVE LOAD
C14
0.1µF
100V
BR2
~
~
+
ISOLATED DC/DC CONVERTER
V
IN
V
IN
V
IN
+
+
+
+
Figure 10. Interfacing Auxiliary Power Source to the PD
42681fc
LTC4268-1
23
to the PSE power. The PD will draw power from the PSE
while the adapter will remain unused. This configuration is
acceptable in a typical PoE system. However, if the adapter
voltage is higher than the PSE voltage, the PD will draw
power from the adapter. In this situation, it is necessary to
address the issue of power cycling that may occur if a PSE
is present. The PSE will detect the PD and apply power. If
the PD is being powered by the adapter, then the PD will
not meet the minimum load requirement and the PSE may
subsequently remove power. The PSE will again detect the
PD and power cycling will start. With an adapter voltage
above the PSE voltage, it is necessary to either disable the
signature as shown in option 2, or install a minimum load
on the output of the LTC4268-1 to prevent power cycling.
A 3k, 1W resistor connected between V
PORTP
and V
NEG
will present the required minimum load.
Option 3 applies power directly to the DC/DC converter
bypassing the LTC4268-1 and omitting diode D9. With
the diode omitted, the adapter voltage is applied to the
LTC4268-1 in addition to the DC/DC
converter. For this
reason,
it is necessary to ensure that the adapter maintain
the voltage between 42V and 57V to keep the LTC4268-1
in its normal operating range. The third option has the
advantage of corrupting the 25k signature resistance when
the external voltage exceeds the PSE voltage and thereby
solving the power priority issue.
Option 4 bypasses the entire PD interface and injects
power at the output of the low voltage power supply. If
the adapter output is below the low voltage output there
are no power priority issues. However, if the adapter is
above the internal supply, then option 4 suffers from the
same power priority issues as option 2 and the signature
should be disabled or a minimum load should be installed.
Shown in option 4 is one method to disable to the signature
while maintaining isolation.
If employing options 1 through 3, it is necessary to ensure
that the end-user cannot access the terminals of the aux-
iliary power jack on the PD since this would compromise
IEEE 802.3af isolation requirements and may violate local
applicaTions inForMaTion
safety codes. Using option 4 along with an isolated power
supply addresses the isolation issue and it is no longer
necessary to protect the end
-user from the power jack.
The
above power cycling scenarios have assumed the
PSE is using DC disconnect methods. For a PSE using
AC disconnect, a PD with less than minimum load will
continue to be powered.
Wall adapters have been known to generate voltage spikes
outside their expected operating range. Care should be
taken to ensure no damage occurs to the LTC4268-1
or any support circuitry from extraneous spikes at the
auxiliary power interface.
Classification Resistor Selection (R
CLASS
)
The IEEE 802.3af specification allows classifying PDs into
four distinct classes with class 4 being reserved for future
use (Table 2). The LTC4268-1 supports all IEEE classes
and implements an additional Class 5 for use in custom
PoE applications. An external resistor connected from
R
CLASS
to V
PORTN
(Figure 6) sets the value of the load
current. The designer should determine which class the
PD is to advertise and then select the appropriate value of
R
CLASS
from Table 2. If a unique load current is required,
the value of R
CLASS
can be calculated as:
R
CLASS
= 1.237V/(I
LOAD
– I
IN_CLASS
)
I
IN_CLASS
is the LTC4268-1 IC supply current during
classification given in the electrical specifications. The
R
CLASS
resistor must be 1% or better to avoid degrading
the overall accuracy of the classification circuit. Resis-
tor power dissipation will be 100mW maximum and is
transient so heating is typically not a concern. In order
to maintain loop stability, the layout should minimize
capacitance at the R
CLASS
node. The classification circuit
can be disabled by floating the R
CLASS
pin. The R
CLASS
pin
should not be shorted to V
PORTN
as this would force the
LTC4268-1 classification circuit to attempt to source very
large currents. In this case, the LTC4268-1 will quickly go
into thermal shutdown.
LTC4268-1
24
42681fc
Power Good Interface
The LTC4268-1 provides complimentary power good
signals to simplify the DC/DC converter interface. Using
the power good signal to delay converter operation until
the load capacitor is fully charged is recommended as this
will help ensure trouble free start-up.
The active high PWRGD pin is controlled by an open col-
lector transistor referenced to V
NEG
while the active low
PWRGD pin is controlled by a high voltage, open-drain
MOSFET referenced to V
PORTN
. The PWRGD pin is de-
signed to interface directly to the UVLO pin with the aid
of a pull-up resistor to Vcc. An example interface circuit
is shown in Figure 11.
the pin voltage and thus creating hysteresis. As the pin
voltage drops below this threshold, the current is disabled,
further dropping the UVLO pin voltage. If not used, the
UVLO pin can be disabled by tying to V
CC
.
Shutdown Interface
To disable the 25k signature resistor, connect SHDN to
the V
PORTP
pin. Alternately, the SHDN pin can be driven
high with respect to V
PORTN
. Examples of interface circuits
that disable the signature and all LTC4268-1 functions are
shown in Figure 10, options 2 and 4. Note that the SHDN
input resistance
is relatively large and the threshold volt-
age is fairly low. Because of high voltages present on the
printed circuit board, leakage currents from the V
PORTP
pin
could inadvertently pull SHDN high. To ensure trouble-free
operation, use high voltage layout techniques in the vicinity
of SHDN. If unused, connect SHDN directly to V
PORTN
.
Load Capacitor
The IEEE 802.3af specification requires that the PD maintain
a minimum load capacitance ofF. It is permissible to
have a much larger load capacitor and the LTC4268-1 can
charge very large load capacitors before thermal issues
become a problem. However, the load capacitor must not
be too large or the PD design may violate IEEE 802.3af
requirements. If the load capacitor is too large, there can
be a problem with inadvertent power shutdown by the PSE.
For example, if the PSE is running at –57V (IEEE 802.3af
maximum allowed) and the PD is detected and powered
up, the load capacitor will be charged to nearly –57V. If
for some reason the PSE voltage is suddenly reduced to
–44V (IEEE 802.3af minimum allowed), the input bridge
will reverse bias and the PD power will be supplied by the
load capacitor. Depending on the
size of the load capacitor
and
the DC load of the PD, the PD will not draw any power
from the PSE for a period of time. If this period of time
exceeds the IEEE 802.3af 300ms disconnect delay, the
PSE will remove power from the PD. For this reason, it
is necessary to evaluate the load current and capacitance
to ensure that inadvertent shutdown cannot occur. Refer
also to Thermal Protection in this data sheet for further
discussion on load capacitor selection.
applicaTions inForMaTion
V
PORTP
V
CC
4k
PWRGD
–54V
42681 F11
TO
PSE
LTC4268-1
ACTIVE-HIGH ENABLE
V
PORTN
UVLO
100k
Figure 11. Power Good Interface Example
Port Voltage Lockout
PoE applications require the PD interface to turn on below
42V and turn off above 30V. The LTC4268-1 includes an
internal port voltage lockout circuit to implement this basic
chip on/off control. Additionally, the LTC4268-1 includes
an enable/lockout function for the DC/DC converter that
is controlled by the UVLO pin and is intended to be driven
by PWRGD to ensure proper start-up. (Refer to Power
Good Interface.) Users have the ability to implement
higher turn-on voltages if necessary by connecting the
UVLO pin to an external resistive divider between V
PORTP
and V
PORTN
. The UVLO pin also includes a bias current
allowing implementation of hysteresis. When UVLO is
below 1.24V, gate drivers are disabled and the converter
sits idle. When the pin rises above the lockout threshold
a small current is sourced out of the UVLO pin, increasing

LTC4268IDKD-1#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Power Switch ICs - POE / LAN EEE 802.3af High Power PD with Synchronous NoOpto Flyback Controller
Lifecycle:
New from this manufacturer.
Delivery:
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