LTC4268IDKD-1#TRPBF Datasheet LTC4268IDKD-1#PBF, LTC4268CDKD-1#TRPBF, LTC4268IDKD-1#TRPBF | P34-P36

LTC4268-1

42681fc

minimum on time along with synchronous rectification

sets the switch over to forced continuous mode operation.

The t

ON(MIN)

resistor is set with the following equation

tON(MIN)

( )

ON(MIN)

( )

−104

1.063

Keep R

tON(MIN)

greater than 70k. A good starting value

is 160k.

Enable Delay Time (ENDLY)

Enable delay time provides a programmable delay between

turn-off of the primary gate drive node and the subsequent

enabling of the feedback amplifier. As discussed earlier, this

delay allows the feedback amplifier to ignore the leakage

inductance voltage spike on the primary side. The worst-case

leakage spike pulse width is at maximum load conditions.

So set the enable delay time at these conditions.

While the typical applications for this part use forced

continuous operation, it is conceivable that a secondary

side controller might cause discontinuous operation at

light loads. Under such conditions the amount of energy

stored in the transformer is small. The flyback waveform

becomes “lazy” and some time elapses before it indicates

the actual secondary output voltage. The enable delay time

should be made long enough to ignore the “irrelevant”

portion of the flyback waveform at light loads.

Even though the LTC4268-1 has a robust gate drive, the

gate transition time slows with very large MOSFETs. In-

crease delay time as required when using such MOSFETs.

The enable delay resistor is set with the following equation:

ENDLY

( )

ENDLY

( )

− 30

2.616

Keep R

ENDLY

greater than 40k. A good starting point is 56k.

Primary Gate Delay Time (PGDLY)

Primary gate delay is the programmable time from the

turn-off of the synchronous MOSFET to the turn-on of

the primary side MOSFET. Correct setting eliminates

overlap between the primary side switch and secondary

side synchronous switch(es) and the subsequent current

spike in the transformer. This spike will cause additional

component stress and a loss in regulator efficiency.

The primary gate delay resistor is set with the following

equation:

PGDLY

( )

PGDLY

( )

+ 47

9.01

A good starting point is 27k.

Soft-Start Function

The LTC4268-1 contains an optional soft-start function that

is enabled by connecting an external capacitor between

the SFST pin and ground. Internal circuitry prevents the

control voltage at the V

CMP

pin from exceeding that on

the SFST pin. There is an initial pull-up circuit to quickly

bring the SFST voltage to approximately 0.8V. From there it

charges to approximately 2.8V with a 20µA current source.

The SFST node is discharged to 0.8V when a fault occurs.

A fault occurs when V

is too low (undervoltage lockout),

current sense voltage is greater than 200mV or the IC’s

thermal (over temperature) shutdown is tripped. When

SFST discharges, the V

CMP

node voltage is also pulled low

to below the minimum current voltage. Once discharged

and the fault removed, the SFST charges up again. In this

manner, switch currents are reduced and the stresses in

the converter are reduced during fault conditions.

The time it takes to fully charge soft-start is:

SFST

• 1.4V

20µA

= 70kW • C

SFST

µF

( )

applicaTions inForMaTion

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LTC4268-1

Converter Start-Up

The standard topology for the LTC4268-1 utilizes a third

transformer winding on the primary side that provides

both feedback information and local V

power for the

LTC4268-1 (see Figure 16). This power “bootstrapping”

improves converter efficiency but is not inherently self-

starting. Start-up is affected with an external “trickle charge”

resistor and the LTC4268-1’s internal V

undervoltage

lockout circuit. The V

undervoltage lockout has wide

hysteresis to facilitate start-up.

In operation, the “trickle charge” resistor R

is connected

to V

and supplies a small current, typically on the order

of 1mA to charge C

. Initially the LTC4268-1 is off and

draws only its start-up current. When C

reaches the

turn-on threshold voltage the LTC4268-1 turns on

abruptly and draws its normal supply current.

Switching action commences and the converter begins to

deliver power to the output. Initially the output voltage is

low and the flyback voltage is also low, so C

supplies

most of the LTC4268-1 current (only a fraction comes

from R

.) V

voltage continues to drop until after some

time, typically tens of milliseconds, the output voltage

approaches its desired value. The

flyback winding

then

provides the LTC4268-1 supply current and the V

voltage stabilizes.

applicaTions inForMaTion

If C

is undersized, V

reaches the V

turn-off threshold

before stabilization and the LTC4268-1 turns off. The V

node then begins to charge back up via R

to the turn-on

threshold, where the part again turns on. Depending upon

the circuit, this may result in either several on-off cycles

before proper operation is reached, or permanent relaxation

oscillation at the V

node.

is selected to yield a worst-case minimum charging

current greater than the maximum rated LTC4268-1 start-

up current, and a worst-case maximum charging current

less than the minimum rated LTC4268-1 supply current.

TR(MAX)

IN(MIN)

− V

CC(ON _ MAX)

CC(ST _ MAX)

and

TR(MIN)

IN(MAX)

− V

CC(ON _ MIN)

CC(MIN)

Make C

large enough to avoid the relaxation oscillatory

behavior described above. This is complicated to deter-

mine theoretically as it depends on the particulars of the

secondary circuit and load behavior. Empirical testing is

recommended. Note that the use of the optional soft-start

function lengthens the power-up timing and requires a

correspondingly larger value for C

VCC

42681 F16

VCC

THRESHOLD

LTC4268-1 PG

GND

•

Figure 16. Typical Power Bootstrapping

LTC4268-1

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applicaTions inForMaTion

The LTC4268-1 has an internal clamp on V

of approxi-

mately 20V. This provides some protection for the part

in the event that the switcher is off (UVLO low) and the

node is pulled high. If R

is sized correctly the part

should never attain this clamp voltage.

Control Loop Compensation

Loop frequency compensation is performed by connect-

ing a capacitor network from the output of the feedback

amplifier (V

CMP

pin) to ground as shown in Figure 17.

Because of the sampling behavior of the feedback amplifier,

compensation is different from traditional current mode

controllers. Normally only C

VCMP

is required. R

VCMP

can

be used to add a “zero” but the phase margin improve-

ment traditionally offered by this extra resistor is usually

already accomplished by the nonzero secondary circuit

impedance. C

VCMP2

can be used to add an additional high

frequency pole and is usually sized at 0.1 times C

VCMP

In further contrast to traditional current mode switchers,

CMP

pin ripple is generally not an issue with the LTC4268-1.

The dynamic nature of the clamped feedback amplifier

forms an effective track/hold type response, whereby the

CMP

voltage changes during the flyback pulse, but is then

“held” during the subsequent “switch on” portion of the

next cycle. This action naturally holds the V

CMP

voltage

stable during the current comparator sense action (current

mode switching).

Application Note 19 provides a method for empirically

tweaking frequency compensation. Basically it involves

introducing a load current step and monitoring the

response.

Slope Compensation

The LTC4268-1 incorporates current slope compensation.

Slope compensation is required to ensure current loop

stability when the DC is greater than 50%. In some switching

regulators, slope compensation reduces the maximum peak

current at higher duty cycles. The LTC4268-1 eliminates

this problem by having circuitry that compensates for

the slope compensation so that maximum current sense

voltage is constant across all duty cycles.

Minimum Load Considerations

At light loads, the LTC4268-1 derived regulator goes into

forced continuous conduction mode. The primary side

switch always turns on for a short time as set by the

ON(MIN)

resistor. If this produces more power than the

load requires, power will flow back into the primary during

the “off” period when the synchronization switch is on.

This does not produce any inherently adverse problems,

although light load efficiency is reduced.

Maximum Load Considerations

The current mode control uses

the V

CMP

node voltage and

amplified sense resistor voltage as inputs to the current

comparator. When the amplified sense voltage exceeds the

CMP

node voltage, the primary side switch is turned off.

In normal use, the peak switch current increases while

FB is below the internal reference. This continues until

CMP

reaches its 2.56V clamp. At clamp, the primary side

MOSFET will turn off at the rated 100mV V

SENSE

level. This

repeats on the next cycle. It is possible for the peak primary

switch currents as referred across R

SENSE

to exceed the

VCMP

CMP

VCMP

42681 F17

VCMP2

Figure 17. V

CMP

Compensation Network

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LTC4268IDKD-1#TRPBF

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Manufacturer:

Analog Devices Inc.

Description:

Power Switch ICs - POE / LAN EEE 802.3af High Power PD with Synchronous NoOpto Flyback Controller

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LTC4268IDKD-1#TRPBF

LTC4268IDKD-1#TRPBF

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