42681fc
LTC4268-1
43
Typical applicaTion
R
tON
100k
R
CLASS
R
SENSE
0.015Ω
1/8W
1%
Q3
Si4488DY
Q4
Si4362DY
R10
91Ω
R20
3.01k
1%
R13
29.4k
1%
C18
22µF
16V
R9
20k
1/4W
C19
0.1µF
D11
BAS21
R
CMP
2.1k
R
ENDLY
150k
R27
10k
C26
680pF
R28
10k
R22
15Ω
R15
47Ω
R8
10Ω
1/4W
R2
10Ω
R13
B0540W
T2
PA0184
D14
BAT54
R17
330Ω
C
OSC
33pF
C1A
12µF
100V
C8
0.1µF
100V
D1
SMAJ58A
C1B
2.2µF
100V
C
CMP
0.1µF
C33
3300pF
C28
2200pF
C23
4700pF
250VAC
Q7
FMMT718
Q6
FMMT618
C11
220pF
C27
0.1µF
C24
1µF
C21
47µF
×2
C22
100µF
3.3V
4A
L3
0.33µH
T1
PA1558NL
42681 TA02
t
ON
R
PGDLY
15k
PGDLY
V
NEG
V
NEG
V
NEG
S2B
C
SFST
0.033µF
SYNC
R
CLASS
SHDN
SENSE
V
CMP
SENSE
+
R
CMP
ENDLY OSC SFST
LTC4268-1
GND
SG
V
PORTP
PWRGD UVLO PGV
CC
I
LIM_EN
FB
C
CMP
PWRGD
L2
4.7µH
L1
0.33µH
C7
1000pF
100V
+
+
C6
100µF
Q2
Si4488DY
11.8V
0.27A
C10
22µF
×2
R3
10Ω
1/4W
C4
1500pF
Q1
Si4470EY
C5
47µF
5V
2.4A
+
+
+
+
+
100k
V
PORTN
V
PORTN
V
PORTN
16
14
15
1
R6
75Ω
R14
4.7k
R18
100k
R21
20k
R5
75Ω
C14
0.01µF
200V
R4
75Ω
24V 30W
AUX POWER IN
J3
C13
0.01µF
200V
C15
0.01µF
200V
C16
0.01µF
200V
C44
0.001µF
2kV
R7
75Ω
3
2
RX
6
RX
+
3
TX
2
TX
+
J1
–54V IN FROM
HIGH POWER PSE
RJ45
T3
ETH1–230LD
XFMR
1
7
8
5
4
11
9
10
6
8
7
TO
PHY
SPARE
SPARE
+
0.1µF
100V
V
PORTP
D2
D3 D4
D5
D6
D7 D8
B2100X8
Q5
FMMT723
10Ω
D9
30W High Efficiency Triple Output PD Supply (Order Demo Circuit DC1080A)
LTC4268-1
44
42681fc
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WXXX)
IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
PIN 1
TOP MARK
(SEE NOTE 6)
BOTTOM VIEW—EXPOSED PAD
R = 0.115
TYP
0.20 ±0.05
116
17 32
6.00 REF
6.43 ±0.10
2.65 ±0.10
4.00 ±0.10
0.75 ±0.05
0.00 – 0.050.200 REF
7.00 ±0.10
(DKD32) QFN 0707 REV A
0.40 BSC
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45° CHAMFER
6.43 ±0.05
2.65 ±0.05
0.70 ±0.05
0.40 BSC
6.00 REF
3.10 ±0.05
4.50 ±0.05
0.40 ±0.10
0.20 ±0.05
PACKAGE
OUTLINE
R = 0.05
TYP
DKD Package
32-Lead Plastic DFN (7mm × 4mm)
(Reference LTC DWG # 05-08-1734 Rev A)
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
42681fc
LTC4268-1
45
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision hisTory
REV DATE DESCRIPTION PAGE NUMBER
C 08/12 Simplified Overview section, including removal of Figure 1A and 1B which caused renumbering of all figures in
data sheet
13, 14
Changed maximum power levels for class 0 and class 3 to 13.0W 15
Added 10Ω resistor to V
PORTP
pin on schematic to make solution more robust to current surges 20, 43
Added Input Capacitor, Input Series Resistance and Transient Voltage Supressor sections 21
Added C14 and 10Ω resistor layout recommendation 41
(Revision history begins at Rev C)

LTC4268IDKD-1#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Power Switch ICs - POE / LAN EEE 802.3af High Power PD with Synchronous NoOpto Flyback Controller
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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