MT90863AG2 Datasheet MT90863AG, MT90863AL1, MT90863AG2 | P1-P3

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

Features

•2,048  512 and 512 x 512 switching among

backplane and local streams

• Rate conversion between 2.048, 4.096 and

8.192 Mb/s

• Optional sub-rate switch configuration for

2.048 Mb/s streams

• Per-channel variable or constant throughput

delay

• Compatible to HMVIP and H.100 specifications

• Automatic frame offset delay measurement

• Per-stream frame delay offset programming

• Per-channel message mode

• Per-channel direction control

• Per-channel high impedance output control

• Non-multiplexed microprocessor interface

• Connection memory block programming

• 3.3 V local I/O with 5 V tolerant inputs and

TTL-compatible outputs

• IEEE-1149.1 (JTAG) Test Port

Applications

• Medium and large switching platforms

• CTI application

• Voice/data multiplexer

• Support ST-BUS, HMVIP and H.100 interfaces

September 2011

Ordering Information

MT90863AG 144 Pin PBGA Trays

MT90863AL1 128 Pin MQFP* Tubes

MT90863AG2 144 Pin PBGA** Trays, Bake & Drypack

*Pb Free Matte Tin

**Pb Free Tin/Silver/Copper

-40C to +85C

MT90863

3 V Rate Conversion Digital Switch

Data Sheet

Figure 1 - Functional Block Diagram

F0o DS CS R/W A7-A0 DTA D15-D0

C16i

Test Port

Output

Mux

Microprocessor Interface

Timing

Unit

Internal

Backplane

Connection

Data Memory

ODE

TDi TDo

RESET

TCK

TRST

TMS

Interface

Backplane

Converter

P/S

S/P

F0i

C4i/C8i

C4o

STo0

STo11

STo12

STo13

STo15

STi0

STi11

STi12

STi13

STi15

(2,048 channels)

(2,048 locations)

Local

Memory High/Low

(512 locations)

Multiple Buffer

Data Memory

(512 channels)

Multiple Buffer

Data Memory

(512 channels)

Registers

IC1

ODE

P/S

Converter

Local

Interface

S/P

Converter

Local

Interface

STio0/

STio15/

FEi15

FEi0

STio16/

STio23/

FEi23

FEi16

STio24

STio31

IC2

Connection

Memory

Multiple Buffer

MT90863 Data Sheet

Zarlink Semiconductor Inc.

Description

The MT90863 Rate Conversion Switch provides switching capacities of 2,048  512 channels between backplane

and local streams, and 512 x 512 channels for local streams. The connected serial inputs and outputs may have 32,

64 and 128 64 kb/s channels per frame with data rates of 2.048 Mb/s, 4.096 Mb/s and 8.192 Mb/s respectively.

The MT90863 also offers a sub-rate switching configuration which allows 2-bit wide 16 kb/s data channels to be

switched within the device.

The device has features (such as: message mode; input and output offset delay; direction control; and, high

impedance output control) that are programmable on per-stream or per-channel basis.

Change Summary

Changes from the May 2006 issue to the September 2011 issue.

Page Item Change

1 Ordering Information Removed leaded packages as per PCN notice.

MT90863 Data Sheet

Table of Contents

Zarlink Semiconductor Inc.

1.0 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.1 Frame Alignment Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.0 Switching Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.1 Backplane Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.2 Local Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.3 Input Frame Offset Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.4 Output Advance Offset Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.5 Serial Input Frame Alignment Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.6 Memory Block Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.0 Delay through the MT90863 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.1 Variable Delay Mode (LV/C or BV/C bit = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.2 Constant Delay Mode (LV/C bit or BV/C= 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.0 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.1 Memory Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.2 Address Buffer Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.3 Write Operation using Address Buffer Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.4 Read Operation using Address Buffer Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.5 Backplane Connection Memory Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.6 Local Connection Memory Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.7 DTA Data Transfer Acknowledgment Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.0 Initialization of the MT90863 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.0 JTAG Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.1 Test Access Port (TAP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.2 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.3 Test Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P46

MT90863AG2

Mfr. #:

Buy MT90863AG2

Manufacturer:

Microchip / Microsemi

Description:

Digital Bus Switch ICs Pb Free RATE CONVERSION DIGITAL SWITCH

Lifecycle:

New from this manufacturer.

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MT90863AG2

MT90863AG2

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