MT90863 Data Sheet
21
Zarlink Semiconductor Inc.
5.6 Local Connection Memory Control
The local connection memory controls the local interface switching configuration. Local connection memory is split
into high and low parts. Locations in local connection memory are associated with particular STo output streams.
The L/B (Local/Backplane Select) bit of each local connection memory location allows per-channel selection of
source streams from local or backplane interface.
The LV
/C (Variable/Constant Delay) bit of each local connection memory location allows the per-channel selection
between variable and constant throughput delay modes for all STo channels.
In message mode, the local connection memory message channel (LMC) bit enables (if high) an associated STo
output channel. If the LMC bit is low, the contents of the stream address bit (LSAB) and the channel address bit
(LCAB) of the local connection memory defines the source information (stream and channel) of the time-slot that
will be switched to the STo streams. When message mode is enabled, only the lower half (8 least significant bits) of
the local connection memory low bits are transferred to the STo pins.
When sub-rate switching is enabled, the LSR0-1 bits in the local connection memory high define which bit position
contains the sub-rate data.
5.7 DTA Data Transfer Acknowledgment Pin
The DTA pin is driven LOW by internal logic to indicate (to the CPU) that a data bus transfer is complete. When the
bus cycle ends, this pin drives HIGH and then switches to the high-impedance state. If a short or signal contention
prevents the DTA
pin from reaching a valid logic HIGH, it will continue to drive for approximately 15nsec before
switching to the high-impedance state.
6.0 Initialization of the MT90863
During power up, the TRST pin should be pulsed low, or held low continuously, to ensure that the MT90863 is in the
normal operation mode. A 5 K pull-down resistor can be connected to this pin so that the device will not enter the
JTAG test mode during power up.
After power up, the contents of the connection memory can be in any state. The ODE pin should be held low after
power up to keep all serial outputs in a high impedance state until the microprocessor has initialized the switching
matrix. This procedure prevents two serial outputs from driving the same stream simultaneously.
During the microprocessor initialization routine, the microprocessor should program the desired active paths
through the switch. The memory block programming feature can also be used to quickly initialize the DC and OE bit
in the backplane and local connection memory respectively.
When this process is complete, the microprocessor controlling the matrices can either bring the ODE pin high or
enable the OSB bit in IMS register to relinquish the high impedance state control.
