MT90863 Data Sheet
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Zarlink Semiconductor Inc.
7.2 Instruction Register
The MT90863 uses the public instructions defined in the IEEE 1149.1 standard. The JTAG Interface contains a two-
bit instruction register. Instructions are serially loaded into the instruction register from the TDi when the TAP
Controller is in its shifted-IR state. These instructions are subsequently de-coded to achieve two basic functions: to
select the test data register that may operate while the instruction is current; and, to define the serial test data
register path that is used to shift data between TDi and DO during data register scanning.
7.3 Test Data Register
As specified in IEEE 1149.1, the MT90863 JTAG Interface contains three test data registers:
• The Boundary-Scan Register
The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path
around the boundary of the MT90863 core logic.
• The Bypass Register
The Bypass register is a single stage shift register that provides a one-bit path from TDi to its TDo.
• The Device Identification Register
The device identification register is a 32-bit register. The register contents are:
The LSB bit in the device identification register is the first bit clock out.
The MT90863 scan register contains 212 bits. Bit 0 in Table 23 Boundary Scan Register is the first bit clocked out.
All tri-state enable bits are active high.
Device Pin
Boundary Scan Bit 0 to Bit 213
Tri-state
Control
Output
Scan Cell
Input
Scan Cell
A0
A1
A2
A3
A4
A5
A6
A7
DS
R/W
CS
0
1
2
3
4
5
6
7
8
9
10
Table 23 - Boundary Scan Register Bits
MSB
LSB
0000 0000 1000 0110 0011 0001 0100 1011
