MT90863 Data Sheet
22
Zarlink Semiconductor Inc.
Bit Name Description
15-10 Unused Must be zero for normal operation.
9-7 BBPD2-0 Backplane Block Programming Data. These bits carry the value to be loaded into
the backplane connection memory block when the Memory Block Programming
feature is active. After the MBP bit in the control register is set to 1 and the BPE bit is
set to 1, the contents of bits BBPD2-0 are loaded into the bit 13 to bit 11 position of the
backplane connection memory. Bit 15, bit 14 and bit 10 to bit 0 of the backplane
connection memory are zeroed.
6-3 LBPD3-0 Local Block Programming Data. These bits carry the value to be loaded into the
local connection memory block when the Memory Block Programming feature is
active. After the MBP bit in the control register is set to 1 and the BPE bit is set to 1,
the contents of bits LBPD3-0 are loaded into the bit 15 to bit 12 position of the local
connection memory. Bit 11 to bit 0 of the local connection memory low are zeroed. Bit
15 to bit 0 of local connection memory high are zeroed.
2 BPE Begin Block Programming Enable. A zero to one transition of this bit enables the
memory block programming function. The BPE, BBPD2-0 and LBPD3-0 bits in the
IMS register must be defined in the same write operation. Once the BPE bit is set
high, the device requires two frames to complete the block programming. After the
programming function has finished, the BPE bit returns to zero to indicate the
operation is completed. When the BPE = 1, the BPE or MBP can be set to 0 to abort
the programming operation.
When BPE = 1, the other bits in the IMS register must not be changed for two frames
to ensure proper operation.
1OSBOutput Stand By. This bit controls the device output drivers.
OSB bit
ODE pin OE bit STio0 - 31, STo0 - 15
0 0 1 High impedance state
1 0 1 Enable
X 1 1 Enable
X X 0 Per-channel high impedance
0SFEStart Frame Evaluation. A zero to one transition in this bit starts the frame evaluation
procedure. When the CFE bit in the FAR register changes from zero to one, the
evaluation procedure stops. Set this bit to zero for at least one frame (125 s) to start
another frame evaluation.
Table 8 - Internal Mode Selection (IMS) Register Bits
Read/Write Address: 02
H
,
Reset Value: 0000
H
.
765432108910111213
LBPDBBPDBBPD
0
1415
LBPD
0
BBPD
BPE OSB SFE
3210
0000
LBPD LBPD
210
