MT90863 Data Sheet
40
Zarlink Semiconductor Inc.
Figure 12 - CT Bus Timing for Stream rate of 2.048, 4.096 or 8.192 Mb/s
t
f
C4i/C8i
t
C8H
t
C8P
t
r
t
f
V
TT
8.192MHz
t
C8L
V
TT
F0o
C4o
4.096MHz
t
FPoW
t
C4L
t
C4H
t
DC4o
t
C4P
V
TT
C16i
ST0/STio (8Mb/s)
STi/STio (8Mb/s)
t
SOD8
t
SIH8
t
CH
t
CP
t
SIS8
V
TT
V
TT
V
HM
V
LM
t
r
t
f
t
f
t
r
t
CL
V
TT
Bit 7, Ch 0
Bit 6, Ch 0 Bit 5, Ch 0
Bit 4, Ch 0
Bit 0, Ch 127Bit 1, Ch 127
Bit 7, Ch 0
Bit 6, Ch 0 Bit 5, Ch 0 Bit 4, Ch 0
Bit 0, Ch 127
Bit 1, Ch 127
16.384MHz
V
TT
V
TT
STo/STio (2Mb/s)
STi/STio (2Mb/s)
Bit 7, Ch 0
Bit 0, Ch 31
t
SOD2
Bit 6, Ch 0
output
input
output
input
V
TT
V
TT
STio (4Mb/s)
STio (4Mb/s)
t
SIH4
t
SIS4
Bit 7, Ch 0Bit 0, Ch63
Bit 7, Ch 0
Bit 6, Ch 0
output
input
Bit 6, Ch 0
Bit 0, Ch 63
t
SOD4
t
SIH2
t
SIS2
Bit 7, Ch 0Bit 0, Ch 31
F0i
t
CFPW
t
CFPH
t
CFPS
V
TT
MT90863 Data Sheet
41
Zarlink Semiconductor Inc.
Figure 13 - HMVIP Bus Timing for Stream rate of 2.048 Mb/s or 8.192 Mb/s
Figure 14 - Serial Output and External Control
F0i
C4i/C8i
4.096MHz
t
HFPW
t
HFPH
t
HFPS
t
DIF
C16i
t
CH
t
CP
V
TT
t
r
t
f
t
Hf
t
Hr
t
CL
V
TT
16.384MHz
t
FPoW
t
C8L
V
TT
F0o
C4o
4.096MHz
t
FPoH
t
FPoS
t
C4L
t
C4H
t
DC4o
t
C4P
V
TT
STio (8Mb/s)
STio (8Mb/s)
t
SOD8
t
SIH8
t
SIS8
V
TT
V
TT
V
HM
V
LM
t
f
t
r
Bit 7, Ch 0
Bit 6, Ch 0 Bit 5, Ch 0
Bit 4, Ch 0
Bit 0, Ch 127
Bit 1, Ch 127
Bit 7, Ch 0
Bit 6, Ch 0 Bit 5, Ch 0
Bit 4, Ch 0
Bit 0, Ch 127
Bit 1, Ch 127
V
TT
V
TT
STio (2Mb/s)
STio (2Mb/s)
Bit 7, Ch 0
Bit 0, Ch 31
t
SOD2
Bit 6, Ch 0
output
input
output
input
t
SIH2
t
SIS2
Bit 7, Ch 0Bit 0, Ch 31
t
HCL
t
HCH
t
DC4o
t
HCP
V
TT
V
HM
V
LM
t
DZ
STo
t
ZD
STo
CLK
V
TT
V
TT
HiZ
Valid Data
V
TT
HiZ
Valid Data
MT90863 Data Sheet
42
Zarlink Semiconductor Inc.
Figure 15 - Output Driver Enable (ODE)
Note:
1. High Impedance is measured by pulling to the appropriate rail with R
L
, with timing corrected to cancel time taken to discharge C
L
.
AC Electrical Characteristics
- Motorola Non-Multiplexed Bus Mode
Characteristics Sym. Min. Typ. Max. Units
Test
Conditions
1CS
setup from DS falling t
CSS
0ns
2R/W
setup from DS falling t
RWS
10 ns
3 Address setup from DS
falling t
ADS
5ns
4CS
hold after DS rising t
CSH
10 ns
5R/W
hold after DS rising t
RWH
10 ns
6 Address hold after DS
rising t
ADH
6ns
7 Data setup from DTA
low on read
Reading registers
Reading Memory
t
DDR_REG
t
DDR_MEM
16
440
ns C
L
=50pF
8 Data hold on read t
DHR
11 ns C
L
=50pF,
R
L
=1K
Note 1
9 Data setup on write (fast write) t
DSW_REG
2ns
10 Valid data delay on write (slow write) t
SWD
150 ns
11 Data hold on write t
DHW
5ns
12 Acknowledgment delay:
Reading/writing registers
Reading/writing memory
t
AKD_REG
t
AKD_MEM
40
470
ns C
L
=50pF
13 Acknowledgment hold time t
AKH
17 ns C
L
=50pF,
R
L
=1K,
Note
V
TT
HiZ
HiZ
STo
ODE
t
ODE
t
ODE
Valid Data
V
TT

MT90863AG2

Mfr. #:
Manufacturer:
Microchip / Microsemi
Description:
Digital Bus Switch ICs Pb Free RATE CONVERSION DIGITAL SWITCH
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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