MT90863AG2 Datasheet MT90863AG, MT90863AL1, MT90863AG2 | P25-P27

MT90863 Data Sheet

Zarlink Semiconductor Inc.

Name

(Note 1)

Description

IFn2, IFn1, IFn0 Input Offset Bits 2,1 & 0. These three bits define how long the serial interface receiver

takes to recognize and store bit 0 from the STio pin: i.e., to start a new frame. The input

frame offset can be selected to +4 clock periods from the point where the external frame

pulse input signal is applied to the F0i

inputs of the device.Figure 9 -

DLEn Data Latch Edge.

ST-BUS mode: DLEn =0, if clock rising edge is at the 3/4 point of the bit cell.

DLEn =1, if clock falling edge is at the 3/4 point of the bit cell.

Table 10 - Frame Delay Offset (DOS) Register Bits

Read/Write Address: 04

for DOS0 register,

for DOS1 register,

for DOS2 register,

for DOS3 register,

for DOS4 register,

for DOS5 register,

Reset value: 0000

for all DOS registers.

765432108910111213

DLE0IF00IF01

IF02

1415

DLE1IF10IF11IF12DLE2IF20IF21IF22DLE3IF30IF31IF32

DOS0 register

DOS1 register

765432108910111213

DLE4IF40IF41

IF42

1415

DLE5IF50IF51IF52DLE6IF60IF61IF62DLE7IF70IF71IF72

DOS2 register

765432108910111213

DLE8IF80IF81

IF82

1415

DLE9IF90IF91IF92DLE10IF100IF101IF102DLE11IF110IF111IF112

DOS3 register

765432108910111213

DLE12IF120IF121

IF122

1415

DLE13IF130IF131IF132DLE14IF140IF141IF142DLE15IF150IF151IF152

DOS4 register

765432108910111213

DLE16IF160IF161

IF162

1415

DLE17IF170IF171IF172DLE18IF180IF181IF182DLE19IF190IF191IF192

DOS5 register

765432108910111213

DLE20IF200IF201

IF202

1415

DLE21IF210IF211IF212DLE22IF220IF221IF222DLE23IF230IF231IF232

MT90863 Data Sheet

Zarlink Semiconductor Inc.

Note 1: n denotes a STio stream number from 0 to 23.

Name

(Note 1)

Description

Table 10 - Frame Delay Offset (DOS) Register Bits

Read/Write Address: 04

for DOS0 register,

for DOS1 register,

for DOS2 register,

for DOS3 register,

for DOS4 register,

for DOS5 register,

Reset value: 0000

for all DOS registers.

765432108910111213

DLE0IF00IF01

IF02

1415

DLE1IF10IF11IF12DLE2IF20IF21IF22DLE3IF30IF31IF32

DOS0 register

DOS1 register

765432108910111213

DLE4IF40IF41

IF42

1415

DLE5IF50IF51IF52DLE6IF60IF61IF62DLE7IF70IF71IF72

DOS2 register

765432108910111213

DLE8IF80IF81

IF82

1415

DLE9IF90IF91IF92DLE10IF100IF101IF102DLE11IF110IF111IF112

DOS3 register

765432108910111213

DLE12IF120IF121

IF122

1415

DLE13IF130IF131IF132DLE14IF140IF141IF142DLE15IF150IF151IF152

DOS4 register

765432108910111213

DLE16IF160IF161

IF162

1415

DLE17IF170IF171IF172DLE18IF180IF181IF182DLE19IF190IF191IF192

DOS5 register

765432108910111213

DLE20IF200IF201

IF202

1415

DLE21IF210IF211IF212DLE22IF220IF221IF222DLE23IF230IF231IF232

MT90863 Data Sheet

Zarlink Semiconductor Inc.

Figure 9 - Examples for Input Offset Delay Timing

Input Stream

Offset

Measurement Result from

Frame Delay Bits

Corresponding

Offset Bits

FD9 FD2 FD1 FD0 IFn2 IFn1 IFn0 DLEn

No clock period shift (Default)10000000

+ 0.5 clock period shift 00000001

+1.0 clock period shift 10010010

+1.5 clock period shift 00010011

+2.0 clock period shift 10100100

+2.5 clock period shift 00100101

+3.0 clock period shift 10110110

+3.5 clock period shift 00110111

+4.0 clock period shift 11001000

+4.5 clock period shift 01001001

Table 11 - Offset Bits (IFn2, IFn1, IFn0, DLEn) & Input Offset Bits (FD9, FD2-0)

ST-BUS F0i

C16i

STio Stream

offset=0, DLE=0

offset=1, DLE=0

offset=0, DLE=1

offset=1, DLE=1

Bit 7

denotes the 3/4 point of the bit cell

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P46

MT90863AG2

Mfr. #:

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MT90863AG2

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