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MT90863AG2

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P46
MT90863 Data Sheet
13
Zarlink Semiconductor Inc.
Figure 6 - HMVIP Mode Timing for 2 and 8 Mb/s Data Streams
3.2 Local Interface
Three operation modes, 2 Mb/s, 8 Mb/s and Sub-rate Switching mode, can be selected for the local interface.
When 2 Mb/s mode is selected, STi0 to STi15 and STo0 to STo15 have a 2.048 Mb/s data rate. When 8 Mb/s mode
is selected, STi0 to STi3 and STo0 to STo3 have an 8.192 Mb/s data rate. When Sub-rate Switching mode is
selected, STi0 to STi11 and STo0 to STo11 have 2.048 Mb/s data with 64 kb/s data channels and STi12 and STo12
have a 2.048 Mb/s data rate with 16 kb/s data channels. Table 3 describes the data rates and mode selection for
the local interface.
3.3 Input Frame Offset Selection
Input frame offset selection allows the channel alignment of individual backplane input streams, that operate at
8.192 Mb/s (STio0-23), to be shifted against the input frame pulse (F0i
). This feature compensates for the variable
path delays caused by serial backplanes of variable length. Such delays can be occur in large centralized and
distributed switching systems.
Each backplane input stream can have its own delay offset value by programming the input delay offset registers
(DOS0 to DOS5). Possible adjustment can range up to +4 master clock (C16i
) periods forward with resolution of
half master clock period. See Table 10 and Table 11, and Figure 9,Figure 9 - for frame input delay offset
programming.
3.4 Output Advance Offset Selection
The MT90863 allows users to advance individual backplane output streams which operate at 8.192 Mb/s (STio0-
23) by half a master clock (C16i
) cycle. This feature is useful in compensating for variable output delays caused by
various output loading conditions. The frame output offset registers (FOR0 & FOR1) control the output offset delays
for each backplane output stream via the OFn bit programming. Table 12 and Figure 10 detail frame output offset
programming.
F0i
C4i/C8i
72345610
0
STio 16 - 23
(8Mb/s mode)
1
2345610
7
Channel 127
Channel 0
F0o
C4o
01 0
STi12/STo12
(Sub-rate
Bit 101
Channel 127
Channel 0
C16i
Switching)
(HMVIP Frame)
(4.096MHz)
0
76
7
0
1
Channel 31
Channel 0
STi/STo 0 - 15
(2Mb/s mode)
STio 0 - 15
MT90863 Data Sheet
14
Zarlink Semiconductor Inc.
3.5 Serial Input Frame Alignment Evaluation
The MT90863 provides the frame evaluation inputs, FEi0 to FEi23, to determine different data input delays with
respect to the frame pulse F0i
. By using the frame evaluation input select bits (FE0 to FE4) of the frame alignment
register (FAR), users can select one of the twenty-four frame evaluation inputs for the frame alignment
measurement.
A measurement cycle is started by setting the start frame evaluation (SFE) bit low for at least one frame. Then the
evaluation starts when the SFE bit in the Internal Mode Selection (IMS) register is changed from low to high. One
frame later, the complete frame evaluation (CFE) bit of the frame alignment register changes from low to high to
signal that a valid offset measurement is ready to be read from bits 0 to 9 of the FAR register. The SFE bit must be
set to zero before a new measurement cycle is started.
Timing Signals ST-BUS Mode CT Bus Mode HMVIP Mode
F0i Width 61 ns 122 ns 244 ns
C4i
/C8i Not Required 8.192 MHz 4.096 MHz
C16i 16.384 MHz
F0o Width 244 ns
C4o 4.096 MHz
Table 1 - Timing Signals Requirements for Various Operation Modes
DMS Register Bits
Modes Backplane Interface Data Rate
BMS2 BMS1 BMS0
0 0 0 2 Mb/s, ST-BUS Mode STio0 - 31 2.048 Mb/s
0 0 1 2 Mb/s, CT Bus Mode STio0 - 31 2.048 Mb/s
0 1 0 4 Mb/s, ST-BUS Mode STio0 - 31 4.096 Mb/s
0 1 1 4 Mb/s, CT Bus Mode STio0 - 31 4.096 Mb/s
1 0 0 8 Mb/s, ST-BUS Mode STio0 - 15 8.192 Mb/s
STio16 - 31 Not available
1 0 1 8 Mb/s, CT Bus Mode STio0 - 15 8.192 Mb/s
STio16 - 31 Not available
1 1 0 HMVIP Mode STio0 - 15 2.048 Mb/s
STio16 - 23 8.192 Mb/s
STio24 - 31 Not available
Table 2 - Mode Selection for Backplane interface
MT90863 Data Sheet
15
Zarlink Semiconductor Inc.
The falling edge of the frame measurement signal (FEi) is evaluated against the falling edge of the frame pulse
(F0i
). Table 8 and Figure 8 describe the frame alignment register.
3.6 Memory Block Programming
The MT90863 has two connection memories: the backplane connection memory and the local connection memory.
The local connection memory is partitioned into high and low parts. The IMS register provides users with the
capability of initializing the local connection memory low and the backplane connection memory in two frames. Bit
11 to bit 13 of every backplane connection memory location will be programmed with the pattern stored in bit 7 to bit
9 of the IMS register. Bit 12 to 15 of every local connection memory low location will be programmed with the
pattern stored in bits 3 to 6 of the IMS register.
The block programming mode is enabled by setting the memory block program (MBP) bit of the control register
high. When the block programming enable (BPE) bit of the IMS register is set to high, the block programming data
will be loaded into bits 11 to 13 of every backplane connection memory and bits 12 to 15 of every local connection
memory low. The other connection memory bits are loaded with zeros. When the memory block programming is
complete, the device resets the BPE bit to zero. See Figure 7 for the connection memory contents when the device
is in block programming mode.
4.0 Delay through the MT90863
The switching of information from the input serial streams to the output serial streams results in a throughput delay.
The device can be programmed to perform time-slot interchange functions with different throughput delay
capabilities on a per-channel basis. For voice applications, select variable throughput delay to ensure minimum
delay between input and output data. In wideband data applications, select constant throughput delay to maintain
the frame integrity of the information through the switch.
The delay through the device varies according to the type of throughput delay selected in the LV
/C and BV/C bits of
the local and backplane connection memory as described in Table 16 and Table 19.
DMS Register Bits
Modes Local Interface Data Rate
LMS1 LMS0
0 0 2 Mb/s Mode STi0 - 15 2.048 Mb/s
STo0 - 15 2.048 Mb/s
01Sub-Rate
Switching
Mode
STi0 - 11 2.048 Mb/s
STi12 Sub-rate Switching Input Stream at 2.048 Mb/s
STi13 - 15 Not available
STo0 - 11 2.048 Mb/s
STo12 Sub-rate Switching Output Stream at
2.048 Mb/s
STo13 - 15 Not available
1 0 8 Mb/s Mode STi0 - 3 8.192 Mb/s
STi4 - 15 Not available
STo0 - 3 8.192 Mb/s
STo4 - 15 Not available
Table 3 - Mode Selection for Local Interface
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P46

MT90863AG2

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Digital Bus Switch ICs Pb Free RATE CONVERSION DIGITAL SWITCH
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