MT90863 Data Sheet
18
Zarlink Semiconductor Inc.
The data in the DMS register consists of the local and backplane mode selection bits (LMS0-1 and BMS0-2) to
enable various switching modes for local and backplane interfaces respectively.
The data in the IMS register consists of block programming bits (LBPD0-3 and BBPD0-2), block programming
enable bit (BPE), output standby bit (OSB) and start frame evaluation bit (SFE). The block programming enable bit
allows users to program the entire backplane and local connection memories, (see Memory Block Programming
section). If the ODE pin is low, the OSB bit enables (if high) or disables (if low) all ST-BUS output drivers. If the ODE
pin is high, the contents of the OSB bit is ignored and all ST-BUS output drivers are enabled.
See Table 5 for the output high impedance control.
5.2 Address Buffer Mode
The implementation of the address buffer, data read and data write registers allows faster memory read/write
operation for the microprocessor port. See Table 6 and following for bit assignments.
The address buffer mode is controlled by the AB bit in the control register. The targeted memory for data read/write
is selected by the MS0-2 bits in the control register.
The data write register (DWR) contains the data to be transferred to the memory. The data read register (DRR)
contains the data transferred from the memory.
The address buffer register (ABR) allow users to specify the read or write address by programming the stream
address bits (SA0-4) and the channel address bits (CA0-6). Data transfer from/to the memory is controlled by the
read/write select bits (RS, WS). The complete data access (CDA) bit indicates the completion of data transfer
between the memory and DWR or DRR register.
5.3 Write Operation using Address Buffer Mode
Enable the address buffer mode by setting the AB bit from low to high. Program the DWR register with data to be
transferred to memory. Load the ABR register with proper channel and stream information. Change the WS bit in
the ABR register from low to high to initiate the data transfer from the DWR register to the memory. After several
master clock cycles, the CDA bit in the ABR register changes from low to high to signal the completion of data
transfer and resets the WS bit to low. Repeat the above steps for subsequent memory write operations. Disable the
address buffer write operation by setting the AB bit to low.
5.4 Read Operation using Address Buffer Mode
Enable the address buffer mode by setting the AB bit from low to high. Program the ABR register with proper
channel and stream information. Change the RS bit in the ABR register from low to high to initiate the data transfer
from the memory to the DRR register. After several master clock cycles, the CDA bit in the ABR register changes
1
1
.
1
1
0
0
.
1
1
1
1
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
1
.
0
1
Ch 32
Ch 33
.
Ch 126
Ch 127
(Note 3)
Notes:
1. Bit A7 must be high for access to data and connection memory positions. Bit A7 must be low for access to registers.
2. Channels 0 to 31 are used when serial stream is at 2 Mb/s.
3. Channels 0 to 127 are used when serial stream is at 8 Mb/s
A7
(Note 1)
A6 A5 A4 A3 A2 A1 A0 Location
Table 4 - Address Memory Map (continued)
