AD9888KSZ-140 Datasheet AD9888KSZ-100, AD9888KSZ-140, AD9888KSZ-170 | P10-P12

Data Sheet AD9888

Rev. C | Page 9 of 36

Table 4. Pin Function Descriptions

Mnemonic Description

Inputs

AIN

0 Channel 0 Analog Input for Red.

AIN

0 Channel 0 Analog Input for Green.

AIN

0 Channel 0 Analog Input for Blue.

AIN

1 Channel 1 Analog Input for Red.

AIN

1 Channel 1 Analog Input for Green.

AIN

1 Channel 1 Analog Input for Blue.

These high impedance inputs accept red, green, and blue channel graphics signals, respectively. The six channels are

identical and can be used for any color; colors are assigned for convenient reference. They accommodate input signals

ranging from 0.5 V to 1.0 V full scale. Signals should be ac-coupled to these pins to support clamp operation.

HSYNC0 Channel 0 Horizontal Sync Input.

HSYNC1 Channel 1 Horizontal Sync Input.

These inputs receive a logic signal that establishes the horizontal timing reference and provides the frequency reference

for pixel clock generation. The logic sense of this pin is controlled by the HSYNC input polarity control (Register 0x0E, Bit 6).

Only the leading edge of HSYNC is used by the PLL. The trailing edge is used for clamp timing only. When the HSYNC input

polarity control = 0, the falling edge of HSYNC is used. When the HSYNC polarity control = 1, the rising edge is active. The

input includes a Schmitt trigger for noise immunity, with a nominal input threshold of 1.5 V.

VSYNC0 Channel 0 Vertical Sync Input.

VSYNC1 Channel 1 Vertical Sync Input.

These are the inputs for vertical sync.

SOGIN0 Channel 0 Sync-on-Green Input.

SOGIN1 Channel 1 Sync-on-Green Input.

These inputs are provided to assist in processing signals with embedded sync, typically on the green channel. These pins

are connected to a high speed comparator with an internally generated, variable threshold level, which is nominally set to

0.15 V above the negative peak of the input signal. When connected to an ac-coupled graphics signal with embedded

sync, these pins produce a noninverting digital output on SOGOUT. This output is usually a composite sync signal,

containing both vertical and horizontal sync information. When not used, these inputs should be left unconnected. For

more details about this function and how it should be configured, see the Sync-on-Green Input section.

CLAMP External Clamp Input.

This logic input can be used to define the time during which the input signal is clamped to the reference dc level (to

ground for RGB or to midscale for YUV). It should be used when the reference dc level is known to be present on the

analog input channels, typically during a period following HSYNC, called the back porch, when a good black reference is

provided. The CLAMP pin is enabled by setting the external clamp control (Register 0x0F, Bit 7) to 1 (default is 0). When

disabled, this pin is ignored and the clamp timing is determined internally by counting a delay and duration from the

trailing edge of the HSYNC input. The logic sense of this pin is controlled by the clamp polarity control (Register 0x0F, Bit 6).

When not used, this pin should be grounded and the external clamp should be programmed to 0.

COAST Clock Generator Coast Input (optional).

This input can be used to stop the pixel clock generator from synchronizing with HSYNC while continuing to produce a

clock at its current frequency and phase. This is useful when processing signals from sources that fail to produce horizontal

sync pulses during the vertical interval or that include equalization pulses. The COAST signal is usually not required for PC

generated signals. The logic sense of this pin is controlled by the coast polarity control (Register 0x0F, Bit 3). When this pin

is not used, either ground the pin and program the coast polarity to 1 or tie the pin high (to V

through a 10 kΩ resistor)

and program the coast polarity to 0. The coast polarity register bit defaults to 1 at power-up.

CKEXT External Clock Input (optional).

This pin can be used to provide an external clock to the AD9888 in place of the clock internally generated from HSYNC. The

external clock is enabled by programming the external clock select bit (Register 0x15, Bit 0) to 1. When an external clock is

used, all other internal functions operate normally. When not used, this pin should be tied through a 10 kΩ resistor to

ground, and the external clock register should be programmed to 0. The clock phase adjustment still operates when an

external clock source is used.

CKINV Sampling Clock Inversion (optional).

This pin can be used to invert the pixel sampling clock, which has the effect of shifting the sampling phase 180°. This

supports the alternate pixel sampling mode, wherein higher frequency input signals (up to 410 MSPS) can be captured by

first sampling the odd pixels, and then capturing the even pixels on the subsequent frame. This pin should be used only

during blanking intervals (typically vertical blanking) because it might produce several samples of corrupted data during

the phase shift. When not in use, this pin should be grounded.

AD9888 Data Sheet

Rev. C | Page 10 of 36

Mnemonic Description

Outputs

[7:0]

Data Output, Red Channel, Port A.

[7:0]

Data Output, Red Channel, Port B.

[7:0]

Data Output, Green Channel, Port A.

[7:0]

Data Output, Green Channel, Port B.

[7:0]

Data Output, Blue Channel, Port A.

[7:0]

Data Output, Blue Channel, Port B.

Each channel has two ports. When the part is operated in single-channel mode (channel mode bit (Register 0x15, Bit 7) = 0),

all data is presented to Port A, and Port B is placed in a high impedance state. Programming the channel mode bit to 1

establishes dual-channel mode, where pixels are alternately presented to Port A and Port B of each channel. These appear

simultaneously; two pixels are presented at the time of every second input pixel when the output mode bit (Register 0x15,

Bit 6) is set to 1 (parallel mode). When the output mode bit is set to 0, pixel data appear alternately on the two ports, one

new sample with each incoming pixel (interleaved mode). In dual-channel mode, the first pixel after HSYNC is routed to

Port A. The second pixel goes to Port B, the third to Port A, and so on. This can be reversed by setting the A/B invert control bit

(Register 0x15, Bit 5) to 1. The delay from the pixel sampling time to the output is fixed. When the sampling time is changed by

adjusting the clock phase adjust register (Register 0x04, Bits[7:3]), the output timing is shifted as well. The DATACK, DATACK,

and HSOUT outputs are also moved; therefore, the timing relationship among the signals is maintained.

DATACK,

DATACK

Data Output Clock, Data Output Clock Complement.

These are differential data clock output signals to be used to strobe the output data and HSOUT into external logic. They

are produced by the internal clock generator and are synchronous with the internal pixel sampling clock. When the AD9888 is

operated in single-channel mode, the output frequency is equal to the pixel sampling frequency. When operated in dual-

channel mode, the clock frequency is half the pixel frequency, as is the output data frequency. When the sampling time is

changed by adjusting the clock phase adjust register (Register 0x04, Bits[7:3]), the output timing is shifted as well. The data,

DATACK, DATACK, and HSOUT outputs are all moved; therefore, the timing relationship among the signals is maintained.

Either or both signals can be used, depending on the timing mode and interface design used.

HSOUT Horizontal Sync Output.

This is a reconstructed, phase-aligned version of the HSYNC input. Both the polarity and duration of this output can be

programmed via serial bus registers. By maintaining alignment with DATACK,

DATACK

, and data, data timing with respect

to horizontal sync can always be determined.

VSOUT Verical Sync Output.

SOGOUT Sync-on-Green (SOG) Slicer Output.

This pin can be programmed to output either the sync-on-green slicer comparator or an unprocessed but delayed version

of the HSYNC input. See the sync processing block diagram (Figure 27) to view how this pin is connected. Note that other

than slicing off SOG, the output from this pin receives no other additional processing on the AD9888. VSYNC separation is

performed via the sync separator.

REF BYPASS Internal Reference Bypass.

The absolute accuracy of this reference is ±4%, and the temperature coefficient is ±50 ppm, which is adequate for most

AD9888 applications. If higher accuracy is required, an external reference can be employed instead.

RMIDSCV Red Channel Midscale Voltage Bypass.

BMIDSCV Blue Channel Midscale Voltage Bypass.

These bypasses for the internal midscale voltage references should each be connected to ground through 0.1 μF capacitors.

The exact voltage varies with the gain setting of the blue channel.

FILT

External Filter Connection. For proper operation, the internal PLL that generates the pixel clock requires an external filter.

Connect the filter shown in Figure 9 to this pin. For optimal performance, minimize noise and parasitics on this node.

Power Supply

Main Power Supply. These pins supply power to the main elements of the circuit. This supply should be as quiet and

filtered as possible.

Digital Output Power Supply.

A large number of output pins (up to 52) switching at high speed (up to 110 MHz) generates significant power supply

transients (noise). These supply pins are identified separately from the V

pins; therefore, special care must be taken to

minimize output noise transferred into the sensitive analog circuitry. If the AD9888 is interfacing with lower voltage logic,

can be connected to a lower supply voltage (as low as 2.5 V) for compatibility.

Clock Generator Power Supply.

The most sensitive portion of the AD9888 is the clock generation circuitry. These pins provide power to the PLL generated pixel

clock and help the user design for optimal performance. The designer should provide noise-free power to these pins.

Data Sheet AD9888

Rev. C | Page 11 of 36

Mnemonic Description

GND Ground.

The ground return for all circuitry on the chip. It is recommended that the AD9888 be assembled on a single solid ground

plane, with careful attention paid to ground current paths.

Serial Port

(2-Wire)

For a full description of the 2-wire serial register and how it works, refer to the 2-Wire Serial Control Port section.

SDA Serial Port Data I/O.

SCL Serial Port Data Clock.

A0 Serial Port Address Input 1

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P37

AD9888KSZ-140

Mfr. #:

Buy AD9888KSZ-140

Manufacturer:

Analog Devices Inc.

Description:

Display Interface IC 140MHz Analog Graphics Interface

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AD9888KSZ-140

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