Data Sheet AD9888
Rev. C | Page 31 of 36
2-WIRE SERIAL CONTROL PORT
A 2-wire serial control interface is provided. Up to two AD9888
devices can be connected to the 2-wire serial interface, with
each device having a unique address.
The 2-wire serial interface comprises a clock (SCL) and a
bidirectional data (SDA) pin. The AD9888 acts as a slave for
receiving and transmitting data over the serial interface. When
the serial interface is not active, the logic levels on SCL and SDA
are pulled high by external pull-up resistors.
Data received or transmitted on the SDA line must be stable for
the duration of the positive-going SCL pulse. Data on SDA must
change only when SCL is low. If SDA changes state while SCL is
high, the serial interface interprets the action as a start or stop
sequence.
There are five components to serial bus operation:
• Start signal
• Slave address byte
• Base register address byte
• Data byte to read or write
• Stop signal
When the serial interface is inactive (SCL and SDA are high),
communications are initiated by sending a start signal. The start
signal is a high-to-low transition on SDA while SCL is high.
This signal alerts all slaved devices that a data transfer sequence
is imminent.
The first eight bits of data transferred after a start signal compose
a 7-bit slave address (the first seven bits) and a single R/
W
bit
(the eighth bit). The R/
W
bit indicates the direction of data
transfer—that is, whether data is being read from (R/
W
= 1) or
written to (R/
W
= 0) the slave device. If the transmitted slave
address matches the address of the device (set by the state of the
A
0
input pin; see ), the acknowledges this by
bringing SDA low on the ninth SCL pulse. If the addresses do
not match, the does not send an acknowledgment.
Table 46 AD9888
AD9888
Table 46. Serial Port Addresses
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
A
6
A
5
A
4
A
3
A
2
A
1
A
0
1 0 0 1 1 0 0
1 0 0 1 1 0 1
BIT 7SDA
SCL
ACKBIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
02442-026
Figure 26. Serial Interface—Typical Byte Transfer
DATA TRANSFER VIA SERIAL INTERFACE
For each byte of data read or written, the MSB is the first bit of
the sequence.
If the AD9888 does not acknowledge the master device during a
write sequence, the SDA remains high so that the master can
generate a stop signal. If the master device does not acknowledge
the AD9888 during a read sequence, the AD9888 interprets this
as being the end of data. The SDA remains high so that the
master can generate a stop signal.
Writing data to a control register of the AD9888 requires writing
to its 8-bit address after the slave address is established. This
control register address is the base address for subsequent write
operations. The base address autoincrements by 1 for each byte
of data written after the data byte intended for the base address.
If more bytes are transferred than there are available addresses,
the address does not increment and remains at its maximum
value of 0x19. Any base address higher than 0x19 does not
produce an acknowledge signal.
Data are read from the control registers of the AD9888 in a
similar manner. Reading requires two data transfer operations.
The base address must be written with the R/
W
bit of the slave
address byte low to set up a sequential read operation.
Reading (with the R/
W
bit of the slave address byte high) begins
at the previously established base address. The address of the
read register autoincrements after each byte is transferred.
To terminate a read/write sequence to the AD9888, a stop signal
must be sent. A stop signal comprises a low-to-high transition
of SDA while SCL is high.
A repeated start signal occurs when the master device driving the
serial interface generates a start signal without first generating a
stop signal to terminate the current communication. This is used to
change the mode of communication (read or write) between the
slave and master without releasing the serial interface lines.
Serial Interface Read/Write Examples
Write to One Control Register
1. Start signal
2. Slave address byte (R/
W
bit = low)
3. Base address byte
4. Data byte to base address
5. Stop signal
Write to Four Consecutive Control Registers
1. Start signal
2. Slave address byte (R/
W
bit = low)
3. Base address byte
4. Data byte to base address
5. Data byte to (base address + 1)
6. Data byte to (base address + 2)
