AD9888KSZ-140 Datasheet AD9888KSZ-100, AD9888KSZ-140, AD9888KSZ-170 | P28-P30

Data Sheet AD9888

Rev. C | Page 27 of 36

Address 0x0F[4]—Coast Input Polarity Override

This bit is used to override the internal circuitry that determines

the polarity of the COAST signal going into the PLL.

Table 22. Coast Input Polarity Override Settings

Coast Input Polarity

Override Setting Function

0 (default) Coast polarity is determined by chip.

1 Coast polarity is determined by user.

Address 0x0F[3]—Coast Input Polarity

This bit indicates the polarity of the COAST signal that is

applied to the PLL coast input.

Table 23. Coast Input Polarity Settings

Coast Input Polarity

Setting Function

0 Active low

1 (default) Active high

Active low means that the clock generator ignores HSYNC

inputs when COAST is low and continues operating at the same

nominal frequency until COAST goes high.

Active high means that the clock generator ignores HSYNC

inputs when COAST is high and continues operating at the

same nominal frequency until COAST goes low.

This function needs to be used along with the coast polarity

override bit (Bit 4).

Address 0x0F[2]—Seek Mode Override

This bit is used to either enable or disable the low power mode.

The low power mode (seek mode) occurs when there are no

signals on any of the sync inputs.

Table 24. Seek Mode Override Settings

Seek Mode Override

Setting Function

0 Disable seek mode

1 (default) Enable seek mode

Address 0x0F[1]—

PWRDN

This bit is used to put the chip into power-down mode. In this

mode, the power dissipation of the chip is reduced to a fraction

of the typical power (see the specifications in Table 1 for exact

power dissipation). When the chip is in power-down mode, the

HSOUT, VSOUT, DATACK,

DATACK

, and all 48 of the data

outputs are put into a high impedance state. Note that the

SOGOUT output is not put into high impedance. Circuit blocks

that continue to be active during power-down mode include the

voltage references, sync processing, sync detection, and the serial

Table 25.

PWRDN

Settings

PWRDN

Setting

Function

0 Power-down

1 (default) Normal operation

Address 0x10[7:3]—Sync-on-Green Slicer Threshold

These bits allow the comparator threshold of the sync-on-green

slicer to be adjusted. The threshold can be adjusted in steps of

10 mV, with a minimum setting of 10 mV and a maximum

setting of 330 mV.

The default setting is 01111, which corresponds to a threshold

value of 0.16 V.

Address 0x10[2]—Red Clamp Select

This bit determines whether the red channel is clamped to

ground or to midscale. For RGB video, all three channels are

referenced to ground. For YCbCr (or YUV), the Y channel is

referenced to ground, but the CbCr channels are referenced to

midscale. Clamping to midscale clamps to Pin 9.

Table 26. Red Clamp Select Settings

Red Clamp Select Setting Function

0 (default) Clamp to ground

1 Clamp to midscale (Pin 9)

Address 0x10[1]—Blue Clamp Select

This bit determines whether the blue channel is clamped to

ground or to midscale. Clamping to midscale clamps to Pin 24.

Table 27. Blue Clamp Select Settings

Blue Clamp Select Setting Function

0 (default) Clamp to ground

1 Clamp to midscale (Pin 24)

Address 0x11[7:0]—Sync Separator Threshold

These bits are used to set the responsiveness of the sync separator.

The bits set how many internal 5 MHz clock periods the sync

separator must count before toggling high or low. This functions

like a low-pass filter to ignore HSYNC pulses to extract the VSYNC

signal. The bits should be set to a number greater than the maxi-

mum HSYNC pulse width. The sync separator threshold uses an

internal dedicated clock with a frequency of approximately 5 MHz.

The default for this register is 0x20.

Address 0x12[7:0]—Pre-COAST

These bits allow the COAST signal to be applied prior to the

VSYNC signal. This is necessary in cases where preequali

zation pulses are present. The step size for this control is one

HSYNC period.

The default is 0.

Address 0x13[7:0]—Post-COAST

This register allows the COAST signal to be applied after the

VSYNC signal. This is necessary in cases where postequali-

zation pulses are present. The step size for this control is one

HSYNC period.

The default setting for each of these bits is 0.

AD9888 Data Sheet

Rev. C | Page 28 of 36

Address 0x14[7]—HSYNC Detect

This bit indicates when activity is detected on the selected

HSYNC input pin. If HSYNC is held high or low, activity is not

detected.

Table 28. HSYNC Detection Results

HSYNC Detect Setting Function

0 No activity detected

1 Activity detected

The sync processing block diagram (Figure 27) shows where

this function is implemented.

Address 0x14[6]—Active HSYNC (AHS)

This bit indicates which horizontal sync input source (HSYNC

or SOG) is used by the PLL (see Table 2 9). When AHS is 0, the

HSYNC pin is used. When AHS is 1, the SOG pin is used.

Determine which source is active by using Bit 7 and Bit 1 in this

and Bit 1 indicates when activity is detected on SOG. If activity

is detected on both HSYNC and SOG, the user can determine

which has priority via Bit 3 in Register 0x0E. The user can

override the function of AHS via Bit 4 in Register 0x0E. If the

override bit is set to Logic 1, AHS is forced to the state that Bit 3

is set to in Register 0x0E.

Table 29. Active HSYNC Settings

Active HSYNC Setting Function

1 SOG pin is used for HSYNC input

0 HSYNC pin is used for HSYNC input

Table 30. Active HSYNC Results

Bit 7 in 0x14

(HSYNC Detect)

Bit 1 in 0x14

(SOG Detect)

Bit 4 in 0x0E

(Override) AHS

0 0 0

N/A (use

Bit 3 in 0x0E)

0 1 0 1

1 0 0 0

1 1 0

N/A (use

Bit 3 in 0x0E)

N/A (use

Bit 3 in 0x0E)

X = don’t care.

Address 0x14[5]—Detected HSYNC Input Polarity Status

This bit reports the status of the HSYNC input polarity detection

circuit. It can be used to determine the polarity of the HSYNC

input. The location of the detection circuit is shown in the sync

processing block diagram (Figure 27).

Table 31. Detected HSYNC Input Polarity Status

Detected HSYNC Input Polarity

Status Setting Function

0 HSYNC polarity is negative.

1 HSYNC polarity is positive.

Address 0x14[4]—VSYNC Detect

This bit is used to indicate when activity is detected on the

selected VSYNC input pin. If VSYNC is held high or low,

activity is not detected.

Table 32. VSYNC Detection Status

VSYNC Detect Setting Function

0 No activity detected

1 Activity detected

The sync processing block diagram (Figure 27) shows where

this function is implemented.

Address 0x14[3]—Active VSYNC (AVS)

This bit indicates which VSYNC source is being used: the

VSYNC input or the output from the sync separator. When AVS

is 1, the sync separator is used. When AVS is 0, the VSYNC

input is used.

Determine which source is active by using Bit 4 and Bit 1 in this

and Bit 1 indicates when activity is detected on SOG. If activity

is detected on both VSYNC and SOG, the user can determine

which has priority via Bit 0 in Register 0x0E. The user can

override the function of AVS via Bit 1 in Register 0x0E. If the

override bit is set to Logic 1, AVS is forced to the state that Bit 0

is set to in Register 0x0E.

Table 33. Active VSYNC Settings

Active VSYNC Setting Function

1 The sync separator is used

0 The VSYNC input is used

Table 34. Active VSYNC Results

Bit 4 in 0x14

(VSYNC Detect)

Bit 1 in 0x14

(SOG Detect)

Bit 1 in 0x0E

(Override) AVS

0 0 0 1

1 1 0 0

N/A (use

Bit 0 in 0x0E)

X = don’t care.

Address 0x14[2]—Detected VSYNC Output Polarity

Status

This bit indicates the status of the VSYNC output polarity

detection circuit and can be used to determine the polarity of

the VSYNC input. The location of the detection circuit is shown

in the sync processing block diagram (Figure 27).

Table 35. Detected VSYNC Input Polarity Status

Detected VSYNC Output Polarity

Status Setting

Function

VSYNC polarity is active

high.

VSYNC polarity is active

low.

Data Sheet AD9888

Rev. C | Page 29 of 36

Address 0x14[1]—Sync-on-Green Detect

This bit indicates when sync activity is detected on the selected

sync-on-green input pin.

Table 36. Sync-on-Green Detection Status

Sync-on-Green Detect Setting Function

0 No activity detected

1 Activity detected

The sync processing block diagram (Figure 27) shows where

this function is implemented.

Address 0x14[0]—Detected Coast Polarity Status

This bit reports the status of the coast input polarity detection

circuit and can be used to determine the polarity of the coast

input. The location of the detection circuit is shown in Figure 27.

Table 37. Detected Coast Input Polarity Status

Detected Coast Polarity

Status Setting Function

0 Coast polarity is negative.

1 Coast polarity is positive.

MODE CONTROL 1

Address 0x15[7]—Channel Mode (DEMUX)

This bit determines whether all pixels are presented to a single

port (Port A) or if pixels are alternately demultiplexed to Port A

and Port B.

Table 38. Output Port Mode Settings

Channel Mode Setting Function

0 All data goes to Port A.

1 (default)

Pixels are alternately presented to

Port A and Port B.

When DEMUX = 0, Port B outputs are in a high impedance

state. The maximum data rate for single-port mode is 110 MHz.

The timing diagrams in Figure 16 to Figure 18 show the effects

of this option.

Address 0x15[6]—Output Mode

This bit determines whether all pixels are presented to Port A

and Port B simultaneously upon every second DATACK rising

edge or if pixels are alternately presented to Port A and Port B

upon successive DATACK rising edges.

Table 39. Output Mode Settings

Output Mode Setting Function

0 Data is interleaved.

1 (default)

Data is simultaneous on every

other data clock.

When in single-port mode (DEMUX = 0), this bit is ignored.

When in dual-port mode, the Figure 19 to Figure 24 timing

diagrams show the effects of this option.

Address 0x15[5]—A/B Invert Control (OUTPHASE)

This bit determines whether even pixels or odd pixels go to Port A.

Table 40. A/B Invert Control Settings

A/B Invert Control Setting First Pixel after HSYNC

0 (default) Port A

1 Port B

In normal operation (OUTPHASE = 0) when operating in dual-

port output mode (DEMUX = 1), the first sample after the HSYNC

leading edge is presented at Port A. Every subsequent odd sample

goes to Port A. All even samples go to Port B.

When OUTPHASE = 1, these ports are reversed and the first

sample goes to Port B.

When DEMUX = 0, this bit is ignored because data always

comes out of only Port A.

Address 0x15[4]—4:2:2 Output Mode Select

This bit configures the output data in 4:2:2 mode. This mode can

be used to reduce the number of data lines used from 24 to 16

for applications using YUV, YCbCr, or YPbPr graphics signals.

A timing diagram for this mode is shown in Figure 25. Recom-

mended input and output configurations are shown in Table 42.

In 4:2:2 mode, the red and blue channels can be interchanged to

help satisfy board layout or timing requirements, but the green

channel must be configured for Y.

Table 41. 4:2:2 Output Mode Select Settings

4:2:2 Output Mode Select

Setting Output Mode

0 (default) 4:4:4

1 4:2:2

Table 42. 4:2:2 Input/Output Configuration

Channel Input Connection Output Format

Red V U/V

Green Y Y

Blue U High impedance

Address 0x15[3]—Input Mux Control

This bit selects analog inputs from either Channel 0 or

Channel 1.

Table 43. Input Mux Control Settings

Input Mux Control Setting Channel Selected

0 (default) Channel 0

1 Channel 1

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P37

AD9888KSZ-140

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Manufacturer:

Analog Devices Inc.

Description:

Display Interface IC 140MHz Analog Graphics Interface

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AD9888KSZ-140

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