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AD9888KSZ-140

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37
Data Sheet AD9888
Rev. C | Page 3 of 36
REVISION HISTORY
12/11—Rev. B to Rev. C
Updated Format..................................................................Universal
Deleted AD9888AKSZ-205 Model .................................. Universal
Changed Maximum Conversion Rate from
205 MSPS to 170 MSPS ............................................ Throughout
Changes to Figure 1 and General Description ..............................1
Deleted AD9888KS-205 Columns, Changes to t
DHO
Parameter,
Table 1.............................................................................................4
Changes to Output Voltage, Low (V
OL
) Parameter, Table 1;
Moved Figure 2..............................................................................5
Changes to Table 2 and ESD Caution Section...............................6
Changes to Table 3 ............................................................................8
Changes to Table 4 ............................................................................9
Changes to YUV Clamping Section and to Gain and Offset
Control Section............................................................................13
Changes to Sync-on-Green Input Section and to Figure 8........14
Changes to Table 5 ..........................................................................15
Moved Figure 10, Figure 11, and Figure 12 .................................16
Changes to Captions of Figure 16 Through Figure 25...............17
Changes to Table 8 ..........................................................................21
Changes to Chip Identification Section .......................................24
Changes to Table 14 and Table 17 .................................................26
Changes to Address 0x10[7:3]—Sync-on-Green Slicer Threshold
Section and to Address 0x11[7:0]—Sync Separator Threshold
Section ..........................................................................................27
Changes to Address 0x14[6]—Active HSYNC (AHS) Section,
Added Table 29, Changes to Address 0x14[3]—Active
VSYNC (AVS) Section, Added Table 33, Changes to
Table 34.........................................................................................28
Changes to Address 0x15[6]—Output Mode Section and to
Address 0x15[5]—A/B Invert Control (OUTPHASE)
Section ..........................................................................................29
Moved Figure 26..............................................................................31
Moved Figure 27..............................................................................32
Changes to Outputs (Both Data and Clocks) Section................34
Changes to Voltage Reference Section .........................................35
Updated Outline Dimensions........................................................36
Changes to Ordering Guide...........................................................36
3/03—Rev. A to Rev. B
Changes to Specifications ...............................................................2
Changes to Pin Configuration.........................................................4
Changes to Table II .........................................................................11
Changes to Table IV........................................................................11
Changes to Figure 20 ......................................................................16
Changes to Figure 22 ......................................................................17
Changes to Table V .........................................................................17
Changes to Table VI........................................................................20
Changes to Table XIII.....................................................................22
Changes to Clamp Input Signal Source Section..........................22
Changes to Table XXX....................................................................24
Added text to Outputs (Both Data and Clocks) Section ...........29
Updated Outline Dimensions........................................................30
1/02—Rev. 0 to Rev. A.
Change to Title–Part Name .............................................................1
Change to Pin Function Detail, CKINV Section..........................7
Change to Figure 13..........................................................................5
Change to Figure 14........................................................................15
Change to Figure 15........................................................................16
Change to Figure 16........................................................................16
Change to Figure 17........................................................................17
Change to Figure 18 .......................................................................17
Change to Figure 21........................................................................19
Change to Figure 22........................................................................19
7/01—Revision 0: Initial Version
AD9888 Data Sheet
Rev. C | Page 4 of 36
SPECIFICATIONS
V
D
= 3.3 V, V
DD
= 3.3 V, ADC clock = maximum conversion rate.
Table 1.
AD9888KSZ-100/-140
1
AD9888KSZ-170
Parameter Temp
Te st
Level Min Typ Max Min Typ Max Unit
RESOLUTION 8 8 Bits
DC ACCURACY
Differential Nonlinearity 25°C I ±0.5 ±1.25/−1.0 ±0.6 +1.25/−1.0 LSB
Full VI +1.35/−1.0 +1.50/−1.0 LSB
Integral Nonlinearity 25°C I ±0.5 ±2.0 ±0.75 ±2.25 LSB
Full VI ±2.5 ±2.75 LSB
No Missing Codes 25°C I Guaranteed Guaranteed
ANALOG INPUT
Input Voltage Range
Minimum 25°C I 0.5 0.5 V p-p
Maximum 25°C I 1.0 1.0 V p-p
Gain Temperature Coefficient 25°C V 100 100 ppm/°C
Input Bias Current 25°C IV 1 1 μA
Full IV 2 2 μA
Input Capacitance Full V 3 3 pF
Input Resistance Full IV 1 1 M
Input Offset Voltage Full VI 7 90 7 90 mV
Input Full-Scale Matching Full VI 2.5 9.0 2.5 9.0 % FS
Offset Adjustment Range Full VI 44 49 53 44 49 53 % FS
REFERENCE OUTPUT
Output Voltage Full VI 1.20 1.25 1.30 1.20 1.25 1.30 V
Temperature Coefficient Full V ±50 ±50 ppm/°C
SWITCHING PERFORMANCE
Maximum Conversion Rate Full VI 100/140 170 MSPS
Minimum Conversion Rate Full IV 10 10 MSPS
Clock to Data Skew (t
skew
) Full IV −1.25 +1.25 −1.25 +1.25 ns
I
2
C Timing
2
t
BUFF
Full VI 4.7 4.7 μs
t
STAH
Full VI 4.0 4.0 μs
t
DHO
Full VI 250 250 ns
t
DAL
Full VI 4.7 4.7 μs
t
DAH
Full VI 4.0 4.0 μs
t
DSU
Full VI 250 250 ns
t
STASU
Full VI 4.7 4.7 μs
t
STOSU
Full VI 4.0 4.0 μs
HSYNC Input Frequency Full IV 15 110 15 110 kHz
Maximum PLL Clock Rate Full VI 100/140 170 MHz
Minimum PLL Clock Rate Full IV 10 10 MHz
PLL Jitter
3
25°C IV 470 700 450 700 ps p-p
Full IV 1000 1000 ps p-p
Sampling Phase Temperature
Coefficient
Full IV 15 15 ps/°C
Data Sheet AD9888
Rev. C | Page 5 of 36
AD9888KSZ-100/-140
1
AD9888KSZ-170
Parameter Temp
Te st
Level
Min Typ Max Min Typ Max Unit
DIGITAL INPUTS Full
Input Voltage, High (V
IH
) Full VI 2.5 2.5 V
Input Voltage, Low (V
IL
) Full VI 0.8 0.8 V
Input Current, High (I
IH
) Full IV −1.0 −1.0 μA
Input Current, Low (I
IL
) Full IV +1.0 +1.0 μA
Input Capacitance 25°C V 3 3 pF
DIGITAL OUTPUTS
Output Voltage, High (V
OH
) Full VI V
D
− 0.1 V
D
− 0.1 V
Output Voltage, Low (V
OL
) Full VI 0.1 V
Duty Cycle Full
DATACK, DATACK
Full IV 44 49 55 44 49 55 %
Output Coding Full IV Binary Binary
POWER SUPPLY
Analog Power Supply Voltage (V
D
) Full IV 3.0 3.3 3.6 3.0 3.3 3.6 V
Output Power Supply Voltage (V
DD
) Full IV 2.2 3.3 3.6 2.2 3.3 3.6 V
PLL Power Supply Voltage (P
VD
) Full IV 3.0 3.3 3.6 3.0 3.3 3.6 V
Analog Power Supply Current (I
D
) 25°C 200 215 mA
Output Power Supply Current (I
DD
)
4
25°C 50 55 mA
PLL Power Supply Current (IP
VD
) 25°C 8 9 mA
Total Power Dissipation Full VI 850 1050 920 1150 mW
Power-Down Supply Current Full VI 12 20 12 20 mA
Power-Down Dissipation Full VI 40 66 40 66 mW
DYNAMIC PERFORMANCE
Analog Bandwidth, Full Power
5
25°C V 500 500 MHz
Transient Response 25°C V 2 2 ns
Overvoltage Recovery Time 25°C V 1.5 1.5 ns
Signal-to-Noise Ratio (SNR)
6
25°C IV 42 45 41 44 dB
Without Harmonics, f
IN
= 40.7 MHz Full V 44 43 dB
Crosstalk Full V 50 50 dBc
THERMAL CHARACTERISTICS
Junction-to-Case Thermal
Resistance (θ
JC
)
V 8.4 8.4 °C/W
Junction-to-Ambient Thermal
Resistance (θ
JA
)
V 35 35 °C/W
1
AD9888JS-100 specifications are tested at 100 MHz. AD9888KS-140 specifications are tested at 140 MHz.
2
See Figure 2.
3
The maximum specifications for the AD9888KS-100 and AD9888KS-140 were obtained with VCO range = 10, charge pump current = 100, PLL divider = 1693. The
maximum specifications for the AD9888KS-170 were obtained with VCO range = 11, charge pump current = 100, PLL divider = 2159.
4
DEMUX = 1, DATACK and
DATACK
load = 15 pF, data load = 5 pF.
5
Maximum bandwidth setting. Bandwidth can also be programmed to 300 MHz, 150 MHz, or 75 MHz.
6
Using an external pixel clock.
t
STAH
t
DHO
t
DSU
t
STASU
t
STOSU
SCL
SDA
t
BUFF
t
DAL
t
DAH
02442-025
Figure 2. Serial Port Read/Write Timing
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37

AD9888KSZ-140

Mfr. #:
Buy AD9888KSZ-140
Manufacturer:
Analog Devices Inc.
Description:
Display Interface IC 140MHz Analog Graphics Interface
Lifecycle:
New from this manufacturer.
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