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AD9888KSZ-140

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37
AD9888 Data Sheet
Rev. C | Page 24 of 36
2-WIRE SERIAL CONTROL REGISTER DETAILS
CHIP IDENTIFICATION
Address 0x00[7:0]—Chip Revision
An 8-bit register that represents the silicon revision.
PLL DIVIDER CONTROL
Address 0x01[7:0]—PLL Divide Ratio MSBs
The eight MSBs of the 12-bit PLL divide ratio (PLLDIV). The
operational divide ratio is PLLDIV + 1.
The PLL derives a master clock from an incoming HSYNC signal.
The master clock frequency is then divided by an integer value,
such that the output is phase locked to HSYNC. This PLLDIV
value determines the number of pixel times (pixels plus horizontal
blanking overhead) per line. This is typically 20% to 30% more
than the number of active pixels in the display.
The 12-bit value of the PLL divider supports divide ratios from
2 to 4095. The higher the value loaded in this register, the higher
the resulting clock frequency with respect to a fixed HSYNC
frequency.
VESA has established standard timing specifications that assist in
determining the value for PLLDIV as a function of horizontal and
vertical display resolution and frame rate (see Table 5). However,
many computer systems do not conform precisely to the recom-
mendations, and these numbers should be used only as a guide.
The display system manufacturer should provide automatic or
manual means for optimizing PLLDIV. An incorrectly set PLLDIV
usually produces one or more vertical noise bars on the display.
The greater the error, the greater the number of bars produced.
The power-up default value of PLLDIV is 1693 (PLLDIVM = 0x69,
PLLDIVL = 0xDx).
The AD9888 updates the full divide ratio only when the LSBs are
changed. Writing to this register by itself does not trigger an update.
Address 0x02[7:4]—PLL Divide Ratio LSBs
The four LSBs of the 12-bit PLL divide ratio (PLLDIV). The
operational divide ratio is PLLDIV + 1.
The power-up default value of PLLDIV is 1693 (PLLDIVM = 0x69,
PLLDIVL = 0xDx).
The AD9888 updates the full divide ratio only when this register is
written to.
CLOCK GENERATOR CONTROL
Address 0x03[7:6]—VCO Range Select
Two bits that establish the operating range of the clock generator.
The VCO range must be set to correspond with the desired
operating frequency (incoming pixel rate).
The PLL provides the best jitter performance at high frequencies.
To output low pixel rates while minimizing jitter, the PLL operates
at a higher frequency and then divides down the clock rate after-
wards. Table 9 shows the pixel rates for each VCO range setting.
The PLL output divisor is automatically selected with the VCO
range setting.
Table 9. VCO Ranges Settings
VCO Range Select Setting Data Clock Range (MHz)
00 10 to 41
01 (default) 41 to 82
10 82 to 150
11 150+
Address 0x03[5:3]—Charge Pump Current
Three bits that establish the current driving the loop filter in the
clock generator. These bits must be set to correspond with the
desired operating frequency (incoming pixel rate).
Table 10. Charge Pump Current Settings
Charge Pump Current Setting Current (mA)
000 50
001 (default) 100
010 150
011 250
100 350
101 500
110 750
111 1500
Address 0x04[7:3]—Clock Phase Adjust
A 5-bit value that adjusts the sampling phase in 32 steps across one
pixel time. Each step represents an 11.25° shift in sampling phase.
The power-up default value is 16.
CLAMP TIMING
Address 0x05[7:0]—Clamp Placement
An 8-bit register that sets the position of the internally
generated clamp.
When the external clamp control bit is set to 0, a CLAMP signal is
generated internally after the trailing edge of HSYNC at a position
(in pixel periods) established by the clamp placement bits and
for a duration (in pixel periods) set by the clamp duration bits.
The clamp placement can be programmed to any value up to
255, except 0.
The clamp should be placed during a time when the input
signal presents a stable black level reference, usually the back
porch period between HSYNC and the image.
When the external clamp control bit is set to 1, this register is
ignored.
Address 0x06[7:0]—Clamp Duration
An 8-bit register that sets the duration of the internally
generated clamp.
When the external clamp control bit is set to 0, a CLAMP signal is
generated internally after the trailing edge of HSYNC at a position
Data Sheet AD9888
Rev. C | Page 25 of 36
(in pixel periods) established by the clamp placement bits and
for a duration (in pixel periods) set by the clamp duration bits.
The clamp duration can be programmed to any value between 1
and 255. A value of 0 is not supported.
For the best results, the clamp duration should be set to include
the majority of the black reference signal time that follows the
HSYNC signal trailing edge. Insufficient clamping time can
produce brightness changes at the top of the screen and a slow
recovery from large changes in the average picture level (APL),
or brightness.
When the external clamp control bit is set to 1, this register is
ignored.
HSYNC PULSE WIDTH
Address 0x07[7:0]—HSYNC Output Pulse Width
An 8-bit register that sets the duration of the HSYNC output pulse.
The leading edge of the HSYNC output is triggered by the
internally generated, phase-adjusted PLL feedback clock. The
AD9888 then counts a number of pixel clocks equal to the value
in this register. This triggers the trailing edge of the HSYNC
output, which is also phase adjusted.
INPUT GAIN
Address 0x08[7:0]—Red Channel Gain Adjust (Red Gain)
An 8-bit word that sets the gain of the red channel.
The AD9888 can accommodate input signals with a full-scale range
between 0.5 V p-p and 1.0 V p-p. Setting red gain to 255 corres-
ponds to an input range of 1.0 V p-p. A red gain of 0 establishes
an input range of 0.5 V p-p. Note that increasing red gain results
in the picture having less contrast because the input signal uses
fewer of the available converter codes (see Figure 5). The same
functionality also applies to the green and blue channel gain
adjust bits.
Address 0x09[7:0]—Green Channel Gain Adjust
(Green Gain)
An 8-bit word that sets the gain of the green channel (see the
Address 0x08[7:0]—Red Channel Gain Adjust (Red Gain)
section for more information).
Address 0x0A[7:0]—Blue Channel Gain Adjust (Blue Gain)
An 8-bit word that sets the gain of the blue channel (see the
Address 0x08[7:0]—Red Channel Gain Adjust (Red Gain)
section for more information).
INPUT OFFSET
Address 0x0B[7:1]—Red Channel Offset Adjust
(Red Offset)
A 7-bit offset binary word that sets the dc offset of the red channel.
One LSB of offset adjustment equals approximately one LSB change
in the ADC offset. Therefore, the absolute magnitude of the offset
adjustment scales as the gain of the channel changes. A nominal
setting of 63 results in the channel nominally clamping to Code 00
during the back porch clamping interval. An offset setting of 127
results in the channel clamping to Code 64 of the ADC. An offset
setting of 0 clamps to Code −63. Increasing the value of red
offset decreases the brightness of the channel. The same
functionality also applies to the green and blue channel offset
adjust bits.
Address 0x0C[7:1]—Green Channel Offset Adjust
(Green Offset)
A 7-bit offset binary word that sets the dc offset of the green
channel (see the Address 0x0B[7:1]—Red Channel Offset
Adjust (Red Offset) section for more information).
Address 0x0D[7:1]—Blue Channel Offset Adjust
(Blue Offset)
A 7-bit offset binary word that sets the dc offset of the blue
channel (see the Address 0x0B[7:1]—Red Channel Offset
Adjust (Red Offset) section for more information).
SYNC CONTROL
Address 0x0E[7]—HSYNC Input Polarity Override
This register is used to override the internal circuitry that
determines the polarity of the HSYNC signal going into the PLL.
Table 11. HSYNC Input Polarity Override Settings
HSYNC Input Polarity
Override Setting Function
0 (default) HSYNC polarity is determined by chip.
1 HSYNC polarity is determined by user.
Address 0x0E[6]—HSYNC Input Polarity
This bit must be set to indicate the polarity of the HSYNC
signal that is applied to the PLL HSYNC input.
Table 12. HSYNC Input Polarity Settings
HSYNC Input Polarity
Setting
Function
0 Active low
1 (default) Active high
Active low means that the leading edge of the HSYNC pulse is
negative-going and, therefore, timing is based on the leading
edge of HSYNC, which is the falling edge. The rising edge has
no effect.
Active high means that the leading edge of the HSYNC pulse is
positive-going and, therefore, timing is based on the leading
edge of HSYNC, which is the rising edge.
Although the device can operate if this bit is set incorrectly, the
internally generated clamp position, as established by the clamp
placement (Register 0x05), will not be placed as expected, which
may generate clamping errors.
AD9888 Data Sheet
Rev. C | Page 26 of 36
Address 0x0E[5]—HSYNC Output Polarity
This bit determines the polarity of the HSYNC output and the
SOG output (see Table 13).
Table 13. HSYNC Output Polarity Settings
HSYNC Output Polarity Setting Function
0 (default) Logic 1 (positive polarity)
1 Logic 0 (negative polarity)
Address 0x0E[4]—Active HSYNC Override
This bit is used to override the automatic HSYNC selection. To
initiate this override, set this bit to Logic 1. When overriding the
automatic HSYNC selection, the active HSYNC is set via Bit 3
in this register.
Table 14. Active HSYNC Override Settings
Active HSYNC Override Setting Function
0 (default)
Bit 6 in Register 0x14 deter-
mines the active interface.
1
Override, Bit 3 determines
the active interface.
Address 0x0E[3]—Active HSYNC Select
This bit is used under two conditions. It is used to select the
active HSYNC when the override bit (Register 0x0E, Bit 4) is
set. Alternatively, it is used to determine the active HSYNC
when the override bit is not set but both HSYNCs are detected.
Table 15. Active HSYNC Select Settings
Active HSYNC Select Setting Function
0 (default) HSYNC input
1 Sync-on-green input
Address 0x0E[2]—VSYNC Output Invert
This bit inverts the polarity of the VSYNC output (see Table 16 ).
Table 16. VSYNC Output Polarity Settings
VSYNC Output Invert Setting Function
0 (default) Invert
1 Do not invert
Address 0x0E[1]—Active VSYNC Override
This bit is used to override the automatic VSYNC selection. To
initiate this override, set this bit to Logic 1. When overriding
the automatic VSYNC selection, the active interface is set via
Bit 0 in this register.
Table 17. Active VSYNC Override Settings
Active VSYNC Override Setting Function
0 (default)
Bit 3 in Register 0x14 deter-
mines the active VSYNC.
1
Override, Bit 0 determines
the active VSYNC.
Address 0x0E[0]—Active VSYNC Select
This bit is used to select the active VSYNC when the override
bit (Register 0x0E, Bit 1) is set.
Table 18. Active VSYNC Select Settings
Active VSYNC Select Setting Function
0 (default) VSYNC input
1 Sync separator output
INPUT CONTROL
Address 0x0F[7]—Clamp Input Signal Source
This bit determines the source of clamp timing.
Table 19. Clamp Input Signal Source Settings
Clamp Input Signal Source Setting Function
0 (default)
Internally generated
clamp
1
Externally provided
clamp signal
A 0 enables the clamp timing circuitry controlled by clamp
placement and clamp duration. The clamp position and
duration is counted from the trailing edge of HSYNC.
A 1 enables the external CLAMP input pin. The three channels are
clamped when the CLAMP signal is active. The polarity of CLAMP
is determined by the clamp input signal polarity bit (Register 0x0F,
Bit 6).
Address 0x0F[6]—Clamp Input Signal Polarity
This bit determines the polarity of the externally provided
CLAMP signal.
Table 20. Clamp Input Signal Polarity Settings
CLAMP Input Signal Polarity Setting Function
0 Active high
1 (default) Active low
A Logic 1 means the circuit clamps when CLAMP is low and
passes the signal to the ADC when CLAMP is high.
A Logic 0 means the circuit clamps when CLAMP is high and
passes the signal to the ADC when CLAMP is low.
Address 0x0F[5]—Coast Select
This bit is used to select the active coast source. The choices are
the COAST input pin or VSYNC. If VSYNC is selected, users
must decide whether to use the VSYNC input pin or the output
from the sync separator (Register 0x0E, Bit 1 and Bit 0).
Table 21. Coast Source Selection Settings
Coast Select Setting Function
0 (default) COAST input pin
1
VSYNC (must choose
VSYNC input pin or
output from sync
separator)
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AD9888KSZ-140

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Manufacturer:
Analog Devices Inc.
Description:
Display Interface IC 140MHz Analog Graphics Interface
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