AD9888 Data Sheet
Rev. C | Page 34 of 36
PCB LAYOUT RECOMMENDATIONS
The AD9888 is a high precision, high speed analog device. To
optimize its performance, it is important to have a well laid out
board. This section provides guidelines for designing a board
using the AD9888.
ANALOG INTERFACE INPUTS
Using the following layout techniques on the graphics inputs is
extremely important.
Minimize the trace length running into the graphics inputs by
placing the AD9888 as close as possible to the graphics (VGA)
connector. Long input trace lengths are undesirable because they
pick up more noise from the board and other external sources.
Place the 75 Ω termination resistors (see Figure 4) as close as
possible to the AD9888 chip. Any additional trace length between
the termination resistors and the input of the AD9888 increases the
magnitude of reflections, which corrupts the graphics signal.
Use 75 Ω matched impedance traces. Trace impedances other
than 75 Ω increase the chance of reflections.
The AD9888 has very high input bandwidth (500 MHz).
Although this is desirable for acquiring a high resolution PC
graphics signal with fast edges, it means that the device also
captures any high frequency noise present. Therefore, it is
important to reduce the amount of noise coupled to the inputs.
Avoid running any digital traces near the analog inputs.
The AD9888 can digitize graphics signals over a very wide range of
frequencies (10 MHz to 170 MHz). Often, characteristics that are
beneficial at one frequency can be detrimental at another. Analog
bandwidth is one such characteristic. For UXGA resolutions
(up to 170 MHz), a very high analog bandwidth is desirable
because of the fast input signal slew rates. For VGA and lower
resolutions (down to 12.5 MHz), a very high bandwidth is not
desirable because it allows excess noise to pass through. To
accommodate these varying needs, the AD9888 includes
variable analog bandwidth control. Four settings are available
(75 MHz, 150 MHz, 300 MHz, and 500 MHz), allowing the
analog bandwidth to be matched with the resolution of the
incoming graphics signal.
POWER SUPPLY BYPASSING
It is recommended to bypass each power supply pin with a
0.1 μF capacitor. The exception is when two or more supply
pins are adjacent to each other. For these groupings of powers/
grounds, it is necessary to have only one bypass capacitor. The
fundamental idea is to have a bypass capacitor within about 0.5 cm
of each power pin. In addition, avoid placing the capacitor on
the side of the PC board opposite from the AD9888 because this
interposes resistive vias in the path.
The bypass capacitors should be physically located between the
power plane and the power pin. Current should flow from the
power plane to the capacitor to the power pin. Do not make the
power connection between the capacitor and the power pin.
Placing a via underneath the capacitor pads, down to the power
plane, is generally the best approach.
It is particularly important to maintain low noise and good stability
of PV
D
(the PLL, VCO supply). Abrupt changes in PV
D
can result
in similarly abrupt changes in sampling clock phase and frequency.
This can be avoided by careful regulation, filtering, and bypassing.
It is highly desirable to provide separate, regulated supplies for
each of the analog circuitry groups, V
D
and PV
D
.
Some graphics controllers use substantially different levels of
power when active (during active picture time) and when idle
(during horizontal and vertical sync periods). This can result in
a measurable change in the voltage supplied to the analog supply
regulator, which can in turn produce changes in the regulated
analog supply voltage. This can be mitigated by regulating the
analog supply, or at least PV
D
, from a different, cleaner power
source, for example, from a 12 V supply.
It is also recommended to use a single ground plane for the entire
board. Experience shows that the noise performance is the same
or better with a single ground plane. Using multiple ground planes
can be detrimental because each separate ground plane is smaller,
and long ground loops can result.
In some cases, using separate ground planes is unavoidable. For
these cases, it is recommended to at least place a single ground
plane under the AD9888. The location of the split should be at
the receiver of the digital outputs, making it even more important
to place components wisely because the current loops will be
much longer, and current takes the path of least resistance. The
following is an example of a current loop signal path: power plane
to AD9888 to digital output trace to digital data receiver to
digital ground plane to analog ground plane.
PLL
Place the PLL loop filter components as close as possible to the
FILT pin. Do not place any digital or other high frequency trace
near these components. Use the values suggested in the data
sheet with 10% tolerances or less.
OUTPUTS (BOTH DATA AND CLOCKS)
Try to minimize the trace length that the digital outputs must
drive. Longer traces have higher capacitance, requiring more
current and causing more internal digital noise. Shorter traces
reduce the possibility of reflections.
Adding a series resistor with a value of 22 Ω to 100 Ω can suppress
reflections, reduce EMI, and reduce the current spikes inside the
AD9888. However, if 50 Ω traces are used on the PCB, the data
output should not need these resistors.
A 22 Ω resistor on the DATACK output should provide good
impedance matching that reduces reflections. If series resistors are
used, place them as close as possible to the AD9888 pins, but
avoid adding vias or extra length to the output trace.
