Data Sheet AD9888
Rev. C | Page 17 of 36
TIMING
Figure 16 through Figure 25 show the operation of the AD9888
analog interface in all clock modes. The part establishes timing
by sending the pixel corresponding with the leading edge of
HSYNC to the A data port. In dual-channel mode, the next sample
is to the B data port. Subsequent samples are alternated between
the A and B data ports. In single-channel mode, data is sent to the
A data port only, and the B data port is placed in a high impedance
state. The output data clock signal is created so that its rising
edge always occurs between transitions of the A port data and
so that it can be used to latch the output data externally.
DATACK
DATACK
RGB DATA OUTPUT
HSOUT
t
SKEW
t
PER
t
DCYCLE
02442-014
Figure 15. Output Timing
HSYNC Timing
Horizontal sync is processed in the AD9888 to eliminate
ambiguity in the timing of the leading edge with respect to
the phase-delayed pixel clock and data.
The HSYNC input is used as a reference to generate the pixel
sampling clock. To optimize the pixel sampling time, the sampling
phase can be adjusted with respect to HSYNC through a full
360° in 32 steps via the clock phase adjust register. Display systems
use HSYNC to align memory and display write cycles; therefore,
it is important to have a stable timing relationship between the
HSYNC output (HSOUT) and data clock (DATACK).
Three things happen to horizontal sync in the AD9888. First,
the polarity of HSYNC input is determined and, therefore, has a
known output polarity. The known output polarity can be
programmed either active high or active low (Register 0x0E, Bit 5).
Second, HSOUT is aligned with DATACK and data outputs. Third,
the duration of HSOUT (in pixel clocks) is set via Register 0x07.
HSOUT is the sync signal that should be used to drive the rest
of the display system.
Coast Timing
In most computer systems, the HSYNC signal is provided
continuously on a dedicated wire. In these systems, the COAST
input and function are unnecessary and should not be used. In
some systems, however, HSYNC is disturbed during the vertical
sync period (VSYNC). In some cases, HSYNC pulses disappear.
In other systems, such as those that use composite sync (Csync)
or embedded sync-on-green (SOG) signals, HSYNC includes
equalization pulses or other distortions during VSYNC. To avoid
upsetting the clock generator during VSYNC, it is important to
ignore these distortions. If the PLL generated pixel clock sees
extraneous pulses, it attempts to lock to this new frequency and
changes frequency by the end of the VSYNC period. It then
requires a few lines of correct HSYNC timing to recover at the
beginning of a new frame, resulting in a “tearing” of the image
at the top of the display.
The COAST input pin is provided to eliminate this problem. It
is an asynchronous input that disables the PLL input and holds
the clock at its current frequency. The PLL can operate in this
manner for several lines without significant frequency drift.
P0 P1 P2 P3 P4 P5 P6 P7
D0 D1 D2 D3 D4
RGB INPUT
HSYNC
PXCK
HS
ADCCK
(INTERNAL)
DATACK
DOUTA
HSOUT
8 PIPELINE DELAY
VARIABLE DURATION
02442-015
Figure 16. Single-Port Mode
