AD9888 Data Sheet
Rev. C | Page 8 of 36
Table 3. Complete Pinout List
Pin Type Mnemonic Description Value Pin No.
Analog Video Inputs R
AIN
0 Channel 0 Analog Input for Converter R. 0.0 V to 1.0 V 5
G
AIN
0 Channel 0 Analog Input for Converter G. 0.0 V to 1.0 V 13
B
AIN
0 Channel 0 Analog Input for Converter B. 0.0 V to 1.0 V 20
R
AIN
1 Channel 1 Analog Input for Converter R. 0.0 V to 1.0 V 8
G
AIN
1 Channel 1 Analog Input for Converter G. 0.0 V to 1.0 V 17
B
AIN
1 Channel 1 Analog Input for Converter B. 0.0 V to 1.0 V 23
Sync/Clock Inputs HSYNC0 Channel 0 Horizontal Sync Input. 3.3 V CMOS 45
VSYNC0 Channel 0 Vertical Sync Input. 3.3 V CMOS 44
SOGIN0 Channel 0 Sync-on-Green Input. 0.0 V to 1.0 V 12
HSYNC1 Channel 1 Horizontal Sync Input. 3.3 V CMOS 43
VSYNC1 Channel 1 Vertical Sync Input. 3.3 V CMOS 42
SOGIN1 Channel 1 Sync-on-Green Input. 0.0 V to 1.0 V 16
CLAMP Clamp Input (external CLAMP signal). 3.3 V CMOS 30
COAST PLL Coast Signal Input. 3.3 V CMOS 53
CKEXT
External Pixel Clock Input (to bypass the PLL), or 10 k
Ω to ground.
3.3 V CMOS 54
CKINV ADC Sampling Clock Invert. 3.3 V CMOS 29
Sync Outputs HSOUT Horizontal Sync Output Clock (phase-aligned with DATACK). 3.3 V CMOS 125
VSOUT Vertical Sync Output Clock (phase-aligned with DATACK). 3.3 V CMOS 127
SOGOUT Sync-on-Green Slicer Output. 3.3 V CMOS 126
Voltage REF BYPASS Internal Reference Bypass (bypass with 0.1 μF to ground). 1.25 V ± 10% 2
Clamp Voltages RMIDSCV Red Channel Midscale Clamp Voltage Bypass. 9
BMIDSCV Blue Channel Midscale Clamp Voltage Bypass. 24
PLL Filter FILT Connection for External Filter Components for Internal PLL. 50
Power Supply V
D
Analog Power Supply. 3.3 V ± 10% 1, 6, 7, 10,
18, 21, 25,
26, 34, 37
V
DD
Output Power Supply. 3.3 V ± 10% 56, 69, 79,
89, 98, 102,
112, 122
PV
D
PLL Power Supply. 3.3 V ± 10% 38, 39, 47,
48, 52
GND Ground. 0 V 3, 4, 11, 15,
19, 22, 27,
28, 35, 36,
40, 41, 46,
49, 51, 55,
65 to 68,
78, 88, 99
to 101,
111, 121,
128
Serial Port SDA Serial Port Data I/O. 3.3 V CMOS 31
(2-Wire Serial Interface) SCL Serial Port Data Clock. 3.3 V CMOS 32
A0 Serial Port Address Input 1. 3.3 V CMOS 33
Data Outputs D
R
A
[7:0]
Port A Outputs of Converter Red. Bit 7 is the MSB. 3.3 V CMOS 113 to 120
D
R
B
[7:0]
Port B Outputs of Converter Red. Bit 7 is the MSB. 3.3 V CMOS 103 to 110
D
G
A
[7:0]
Port A Outputs of Converter Green. Bit 7 is the MSB. 3.3 V CMOS 90 to 97
D
G
B
[7:0]
Port B Outputs of Converter Green. Bit 7 is the MSB. 3.3 V CMOS 80 to 87
D
B
A
[7:0]
Port A Outputs of Converter Blue. Bit 7 is the MSB. 3.3 V CMOS 70 to 77
D
B
B
[7:0]
Port B Outputs of Converter Blue. Bit 7 is the MSB. 3.3 V CMOS 57 to 64
Data Clock Output DATACK Data Output Clock. 3.3 V CMOS 123
DATACK
Data Output Clock Complement. 3.3 V CMOS 124
