AR0330CM
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13
Two-Wire Serial Register Interface
The electrical characteristics of the two-wire serial
register interface (S
CLK
, S
DATA
) are shown in Figure 8 and
Table 14.
Figure 8. Two-Wire Serial Bus Timing Parameters
S
DATA
S
CLK
S Sr P S
t
f
t
r
t
f
t
r
t
SU;DAT
t
HD;STA
t
SU;STO
t
SU;STA
t
BUF
t
HD;DAT
t
HIGH
t
LOW
t
HD;STA
NOTE: Read sequence: For an 8-bit READ, read waveforms start after WRITE command and register address are issued.
Table 14. TWO-WIRE SERIAL BUS CHARACTERISTICS
(f
EXTCLK
= 27 MHz; V
DD
= 1.8 V; V
DD
_IO = 2.8 V; V
AA
= 2.8 V; V
AA
_PIX = 2.8 V; V
DD
_PLL = 2.8 V; T
A
= 25°C)
Parameter
Symbol
Standard Mode Fast Mode
Unit
Min Max Min Max
S
CLK
Clock Frequency t
SCL
0 100 0 400 kHz
Hold Time (Repeated) START Condition
After this Period, the First Clock Pulse is
Generated
t
HD;STA
4.0 − 0.6 −
ms
LOW Period of the S
CLK
Clock t
LOW
4.7 − 1.3 −
ms
HIGH Period of the S
CLK
Clock t
HIGH
4.0 − 0.6 −
ms
Set-up Time for a Repeated START
Condition
t
SU;STA
4.7 − 0.6 −
ms
Data Hold Time t
HD;DAT
0
(Note 4)
3.45
(Note 5)
0
(Note 6)
0.9
(Note 5)
ms
Data Set-up Time t
SU;DAT
250 − 100
(Note 6)
− ns
Rise Time of both S
DATA
and S
CLK
Signals
t
r
− 1000 20 + 0.1 Cb
(Note 7)
300 ns
Fall Time of both S
DATA
and S
CLK
Signals
t
f
− 300 20 + 0.1 Cb
(Note 7)
300 ns
Set-up Time for STOP Condition t
SU;STO
4.0 − 0.6 −
ms
Bus Free Time between a STOP and
START Condition
t
BUF
4.7 − 1.3 −
ms
Capacitive Load for Each Bus Line Cb − 400 − 400 pF
Serial Interface Input Pin Capacitance CIN_SI − 3.3 − 3.3 pF
S
DATA
Max Load Capacitance CLOAD_SD − 30 − 30 pF
S
DATA
Pull-up Resistor RSD 1.5 4.7 1.5 4.7
kW
1. This table is based on I
2
C standard (v2.1 January 2000). Philips Semiconductor.
2. Two-wire control is I
2
C-compatible.
3. All values referred to V
IHmin
= 0.9 V
DD
and V
ILmax
= 0.1 V
DD
levels. Sensor EXCLK = 27 MHz.
4. A device must internally provide a hold time of at least 300 ns for the S
DATA
signal to bridge the undefined region of the falling edge of S
CLK
.
5. The maximum t
HD;DAT
has only to be met if the device does not stretch the LOW period (t
LOW
) of the S
CLK
signal.
6. A Fast-mode I
2
C-bus device can be used in a Standard-mode I
2
C-bus system, but the requirement t
SU;DAT
250 ns must then be met. This
will automatically be the case if the device does not stretch the LOW period of the S
CLK
signal. If such a device does stretch the LOW period
of the S
CLK
signal, it must output the next data bit to the S
DATA
line t
r
max + t
SU;DAT
= 1000 + 250 = 1250 ns (according to the Standard-mode
I
2
C-bus specification) before the S
CLK
line is released.
7. Cb = total capacitance of one bus line in pF.
