AR0330CM
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DATA PEDESTAL
The data pedestal is a constant offset that is added to pixel
values at the end of datapath. The default offset is 168 and
is a 12-bit offset. This offset matches the maximum range
used by the corrections in the digital readout path.
The data pedestal value can be changed if the lock register
bit (R0x301A[3]) is set to “0”. This bit is set to “1” by
default.
SENSOR READOUT
Image Acquisition Modes
The AR0330 supports two image acquisition modes:
• Electronic Rolling Shutter (ERS) Mode:
This is the normal mode of operation. When the
AR0330 is streaming; it generates frames at a fixed
rate, and each frame is integrated (exposed) using the
ERS. When the ERS is in use, timing and control logic
within the sensor sequences through the rows of the
array, resetting and then reading each row in turn. In the
time interval between resetting a row and subsequently
reading that row, the pixels in the row integrate incident
light. The integration (exposure) time is controlled by
varying the time between row reset and row readout.
For each row in a frame, the time between row reset
and row readout is the same, leading to a uniform
integration time across the frame. When the integration
time is changed (by using the two-wire serial interface
to change register settings), the timing and control logic
controls the transition from old to new integration time
in such a way that the stream of output frames from the
AR0330 switches cleanly from the old integration time
to the new while only generating frames with uniform
integration. See “Changes to Integration Time” in the
AR0330 Register Reference.
• Global Reset Mode:
This mode can be used to acquire a single image at the
current resolution. In this mode, the end point of the
pixel integration time is controlled by an external
electromechanical shutter, and the AR0330 provides
control signals to interface to that shutter.
The benefit of using an external electromechanical
shutter is that it eliminates the visual artifacts
associated with ERS operation. Visual artifacts arise in
ERS operation, particularly at low frame rates, because
an ERS image effectively integrates each row of the
pixel array at a different point in time.
Window Control
The sequencing of the pixel array is controlled by the
x_addr_start, y_addr_start, x_addr_end, and y_addr_end
registers. The x_addr_start equal to 6 is the minimum setting
value. The y_addr_start equal to 6 is the minimum setting
value. Please refer to Table 33 and Table 34 for details.
Table 33. PIXEL COLUMN CONFIGURATION
Column Address
Number Type Notes
0–5 6 Active Border columns
6–2309 2304 Active Active columns
2310–2315 6 Active Border columns
Table 34. PIXEL ROW CONFIGURATION
Row Address
Number Type Notes
2–5 4 Active Not used in case of “edge effects”
6–1549 1544 Active Active rows
1550–1555 6 Active Not used in case of “edge effects”
Readout Modes
Horizontal Mirror
When the horizontal_mirror bit (R0x3040[14]) is set in
the image_orientation register, the order of pixel readout
within a row is reversed, so that readout starts from
x_addr_end + 1and ends at x_addr_start. Figure 31 shows
a sequence of 6 pixels being read out with R0x3040[14] = 0
and R0x3040[14] = 1. Changing R0x3040[14] causes the
Bayer order of the output image to change; the new Bayer
order is reflected in the value of the pixel_order register.
