AR0330CM
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22
SEQUENCER
The sequencer digital block determines the order and
timing of operations required to sample pixel data from the
array during each row period. It is controlled by an
instruction set that is programmed into RAM from the
sensor OTPM (One Time Programmable Memory). The
OTPM is configured during production.
The instruction set determines the length of the sequencer
operation that determines the “ADC Readout Limitation”
(Equation 5) listed in the Sensor Frame Rate section. The
instruction set can be shortened through register writes in
order to achieve faster frame rates. Instructions for
shortening the sequencer can be found in the AR0330
Developer Guide.
The sequencer digital block can be reprogrammed using
the following instructions:
Program a new sequencer.
1. Place the sensor in standby.
2. Write 0x8000 to R0x3088 (“seq_ctrl_port”).
3. Write each instruction incrementally to R0x3086.
Each write must be 16-bit consisting of two bytes
{Byte[N], Byte[N+1]}.
4. If the sequencer consists of an odd number of
bytes, set the last byte to “0”.
Read the instructions stored in the sequencer.
1. Place the sensor in standby.
2. Write 0xC000 to R0x3088 (“seq_ctrl_port”).
3. Sequentially read one byte at a time from R0x3086
with 8-bit read command.
SENSOR PLL
VCO
The sensor contains a phase-locked loop (PLL) that is
used for timing generation and control. The required VCO
clock frequency is attained through the use of a pre-PLL
clock divider followed by a multiplier (see Figure 17). The
multiplier is followed by set of dividers used to generate the
output clocks required for the sensor array, the pixel analog
and digital readout paths, and the output parallel and serial
interfaces.
Dual Readout Paths
There are two readout paths within the sensor digital block
(see Figure 18).
The sensor row timing calculations refers to each
data-path individually. For example, the sensor default
configuration uses 1248 clocks per row (line_length_pck) to
output 2304 active pixels per row. The aggregate clocks per
row seen by the receiver will be 2496 clocks (1248 × 2
readout paths).
Figure 17. Relationship between Readout Clock and Peak Pixel Rate
pre_pll_clk_div
2(1−64)
pll_multiplier
58(32−384)
F
VCO
EXTCLK
(6−27 MHz)
Figure 18. Sensor Dual Readout Paths
Pixel Array
All Digital
Blocks
All Digital
Blocks
CLK_PIX
CLK_PIX
Serial Output
(MIPI or HiSPi)
Pixel Rate = 2 × CLK_PIX
= # Data Lanes × CLK_OP (HiSPi or MIPI)
= CLK_OP (Parallel)
