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AR0330CM1C00SHAAH3-GEVB

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P53
AR0330CM
www.onsemi.com
4
TYPICAL CONFIGURATIONS
Figure 2. Serial 4-lane HiSPi Interface
1. All power supplies must be adequately decoupled. ON Semiconductor recommends having 1.0 mF and 0.1 mF decoupling capacitors for
every power supply. If space is a concern, then priority must be given in the following order: V
AA
, V
AA
_PIX, V
DD
_PLL, V
DD
_IO, and V
DD
.
Actual values and results may vary depending on layout and design considerations.
2. To allow for space constraints, ON Semiconductor recommends having 0.1 mF decoupling capacitor inside the module as close to the pads
as possible. In addition, place a 10 mF capacitor for each supply off-module but close to each supply.
3. ON Semiconductor recommends a resistor value of 1.5 kW, but a greater value may be used for slower two-wire speed.
4. This pull-up resistor is not required if the controller drives a valid logic level on S
CLK
at all times.
5. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes is
minimized.
6. TEST pin should be tied to D
GND
.
7. Set High_VCM (R0x306E[9]) to 0 (default) to use the V
DD
_HiSPi_TX in the range of 0.4–0.8 V. Set High_VCM to 1 to use a range of
1.7–1.9 V.
8. The package pins or die pads used for the MIPI data and clock as well as the parallel interface must be left floating.
9. The V
DD
_MIPI package pin and sensor die pad should be connected to a 2.8 V supply as V
DD
_MIPI is tied to the V
DD
_PLL supply both
in the package routing and also within the sensor die itself.
10.If the SHUTTER or FLASH pins or pads are not used, then they must be left floating.
11. If the TRIGGER pin or pad is not used then it should be tied to D
GND
.
12.The GND_SLVS pad must be tied to D
GND
. It is connected this way in the CLCC and CSP packages.
Notes:
SHUTTER
SLVS0_P
SLVS0_N
SLVS1_P
SLVS1_N
SLVS2_P
SLVS2_N
V
DD
_PLLV
DD
_IO V
AA
V
AA
_PIX
A
GND
D
GND
V
AA
_PIXV
AA
V
DD
_IO V
DD
S
DATA
S
CLK
EXTCLK
1.5 kW
3
1.5 kW
3,
4
TRIGGER
OE_BAR
RESET_BAR
TEST
To Controller
(HiSPi-serial
Interface)
From
Controller
Master Clock
(6−27 MHz)
Digital
I/O
Power
1
Digital
Core
Power
1
Analog
Power
1
Analog
Power
1
Analog
Ground
Digital
Ground
V
DD
_HiSPi_TX
HiSPi
Power
1
V
DD
_PLL
PLL
Power
1
SLVS3_P
SLVS3_N
SLVSC_P
SLVSC_N
V
DD
_HiSPi_TX V
DD
V
DD
_HiSPi
GND_SLVS
S
ADDR
V
DD
_MIPI
V
DD
_HiSPi
FLASH
0.1 mF1.0 mF0.1 mF1.0 mF0.1 mF1.0 mF0.1 mF1.0 mF0.1 mF1.0 mF0.1 mF1.0 mF0.1 mF1.0 mF
AR0330CM
www.onsemi.com
5
Figure 3. Serial MIPI
1. All power supplies must be adequately decoupled. ON Semiconductor recommends having 1.0 mF and 0.1 mF decoupling capacitors for
every power supply. If space is a concern, then priority must be given in the following order: V
AA
, V
AA
_PIX, V
DD
_PLL, V
DD
_MIPI, V
DD
_IO,
and V
DD
. Actual values and results may vary depending on layout and design considerations.
2. To allow for space constraints, ON Semiconductor recommends having 0.1 mF decoupling capacitor inside the module as close to the pads
as possible. In addition, place a 10 mF capacitor for each supply off-module but close to each supply.
3. ON Semiconductor recommends a resistor value of 1.5 kW, but a greater value may be used for slower two-wire speed.
4. This pull-up resistor is not required if the controller drives a valid logic level on S
CLK
at all times.
5. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes is
minimized.
6. TEST pin must be tied to D
GND
for the MIPI configuration.
7. ON Semiconductor recommends that GND_MIPI be tied to D
GND
.
8. V
DD
_MIPI is tied to V
DD
_PLL in both the CLCC and the CSP package. ON Semiconductor strongly recommends that V
DD
_MIPI must be
connected to a V
DD
_PLL in a module design since V
DD
_PLL and V
DD
_MIPI are tied together in the die.
9. The package pins or die pads used for the HiSPi data and clock as well as the parallel interface must be left floating.
10.HiSPi Power Supplies (V
DD
_HISPI and V
DD
_HISPI_TX) can be tied to ground.
11. If the SHUTTER or FLASH pins or pads are not used, then they must be left floating.
12.If the TRIGGER pin or pad is not used then it should be tied to D
GND
.
Notes:
FLASH
DATA1_P
DATA1_N
DATA2_P
DATA2_N
DATA3_P
DATA3_N
V
DD
_PLLV
DD
_IO V
AA
V
AA
_PIX
A
GND
D
GND
V
AA
_PIXV
AA
V
DD
_IO V
DD
S
DATA
S
CLK
EXTCLK
1.5 kW
3
1.5 kW
3,
4
TRIGGER
OE_BAR
RESET_BAR
TEST
To Controller
(MIPI-serial
Interface)
From
Controller
Master Clock
(6−27 MHz)
Digital
I/O
Power
1
Digital
Core
Power
1
Analog
Power
1
Analog
Power
1
Analog
Ground
Digital
Ground
V
DD
_PLL
PLL
Power
1
DATA4_P
DATA4_N
CLK_P
CLK_N
V
DD
S
ADDR
V
DD
_MIPI
SHUTTER
0.1 mF1.0 mF0.1 mF1.0 mF0.1 mF1.0 mF0.1 mF1.0 mF0.1 mF1.0 mF
AR0330CM
www.onsemi.com
6
Figure 4. Parallel Pixel Data Interface
1. All power supplies must be adequately decoupled. ON Semiconductor recommends having 1.0 mF and 0.1 mF decoupling capacitors for
every power supply. If space is a concern, then priority must be given in the following order: V
AA
, V
AA
_PIX, V
DD
_PLL, V
DD
_IO, and V
DD
.
Actual values and results may vary depending on layout and design considerations.
2. To allow for space constraints, ON Semiconductor recommends having 0.1 mF decoupling capacitor inside the module as close to the pads
as possible. In addition, place a 10 mF capacitor for each supply off-module but close to each supply.
3. ON Semiconductor recommends a resistor value of 1.5 kW, but a greater value may be used for slower two-wire speed.
4. This pull-up resistor is not required if the controller drives a valid logic level on S
CLK
at all times.
5. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes is
minimized.
6. TEST pin should be tied to the ground.
7. The data and clock package pins or die pads used for the HiSPi and MIPI interface must be left floating.
8. The V
DD
_MIPI package pin and sensor die pad should be connected to a 2.8 V supply as it is tied to the V
DD
_PLL supply both in the
package routing and also within the sensor die itself. HiSPi Power Supplies (V
DD
_HISPI and V
DD
_HISPI_TX) can be tied to ground.
9. If the SHUTTER or FLASH pins or pads are not used, then they must be left floating.
10.If the TRIGGER pin or pad is not used then it should be tied to D
GND
.
Notes:
FRAME_VALID
LINE_VALID
PIXCLK
SHUTTER
V
DD
_IO V
DD
V
AA
V
AA
_PIX
A
GND
D
GND
V
AA
_PIXV
AA
V
DD
_IO V
DD
EXTCLK
S
DATA
S
CLK
1.5 kW
3
1.5 kW
3,
4
TRIGGER
OE_BAR
RESET_BAR
TEST
To Controller
From
Controller
Master Clock
(6−27 MHz)
Digital
I/O
Power
1
Digital
Core
Power
1
Analog
Power
1
Analog
Power
1
Analog
Ground
Digital
Ground
D
OUT
[11:0]
PLL
Power
1
V
DD
_PLL
V
DD
_PLL
0.1 mF1.0 mF 0.1 mF1.0 mF 0.1 mF1.0 mF 0.1 mF1.0 mF 0.1 mF1.0 mF
FLASH
S
ADDR
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P53

AR0330CM1C00SHAAH3-GEVB

Mfr. #:
Buy AR0330CM1C00SHAAH3-GEVB
Manufacturer:
ON Semiconductor
Description:
Optical Sensor Development Tools 3.5 MP 1/3" CIS HB
Lifecycle:
New from this manufacturer.
Delivery:
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