AR0330CM
www.onsemi.com
28
HiSPi Streaming Mode Protocol Layer
The HiSPi protocol is described HiSPi Protocol V1.00.00
A.
MIPI Interface
The serial pixel data interface uses the following
output-only signal pairs:
• DATA1_P
• DATA1_N
• DATA2_P
• DATA2_N
• DATA3_P
• DATA3_N
• DATA4_P
• DATA4_N
• CLK_P
• CLK_N
The signal pairs use both single-ended and differential
signaling, in accordance with the the MIPI Alliance
Specification for D−PHY v1.00.00. The serial pixel data
interface is enabled by default at power up and after reset.
The DATA0_P, DATA0_N, DATA1_P, DATA1_N,
CLK_P and CLK_N pads are set to the Ultra Low Power
State (ULPS) if the serial disable bit is asserted
(R0x301A−B[12] = 1) or when the sensor is in the hardware
standby or soft standby system states.
When the serial pixel data interface is used, the
LINE_VALID, FRAME_VALID, PIXCLK and
D
OUT
[11:0] signals (if present) can be left unconnected.
Serial Configuration
The serial format should be configured using R0x31AC.
This register should be programmed to 0x0C0C when using
the parallel interface.
The R0x0112−3 register can be programmed to any of the
following data format settings that are supported:
• 0x0C0C – Sensor supports RAW12 uncompressed data
format
• 0x0C0A – The sensor supports RAW12 compressed
format (10-bit words) using 12−10 bit A−LAW
Compression. See “Compression” section
• 0x0A0A – Sensor supports RAW10 uncompressed data
format. This mode is supported by discarding all but the
upper 10 bits of a pixel value
• 0x0808 – Sensor supports RAW8 uncompressed data
format. This mode is supported by discarding all but the
upper 8 bits of a pixel value (MIPI only).
The serial_format register (R0x31AE) register controls
which serial interface is in use when the serial interface is
enabled (reset_register[12] = 0). The following serial
formats are supported:
• 0x0201 – Sensor supports single-lane MIPI operation
• 0x0202 – Sensor supports dual-lane MIPI operation
• 0x0204 – Sensor supports quad-lane MIPI operation
• 0x0304 − Sensor supports quad-lane HiSPi operation
The MIPI timing registers must be configured differently
for 10-bit or 12-bit modes. These modes should be
configured when the sensor streaming is disabled. See
Table 31.
Table 31. RECOMMENDED MIPI TIMING CONFIGURATION
Register
Configuration
Description
10-bit, 490 Mbps/Lane 12-bit, 588 Mbps/Lane
Clocking: Continuous
0x31B0 40 36 Frame Preamble
0x31B2 14 12 Line Preamble
0x31B4 0x2743 0x2643 MIPI Timing 0
0x31B6 0x114E 0x114E MIPI Timing 1
0x31B8 0x2049 0x2048 MIPI Timing 2
0x31BA 0x0186 0x0186 MIPI Timing 3
0x31BC 0x8005 0x8005 MIPI Timing 4
0x31BE 0x2003 0x2003 MIPI Config Status
