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AR0330CM1C00SHAAH3-GEVB

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AR0330CM
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16
Table 20. SLVS ELECTRICAL TIMING SPECIFICATION
Symbol
Parameter Min Max Unit
1/UI
Data Rate (Note 1)
280 700 Mbps
t
PW
Bitrate Period (Note 1)
1.43 3.57 ns
t
PRE
Max Setup Time from Transmitter (Notes 1, 2)
0.3 − UI
t
POST
Max Hold Time from Transmitter (Notes 1, 2)
0.3 − UI
t
EYE
Eye Width (Notes 1, 2)
− 0.6 UI
t
TOTALJIT
Data Total Jitter (pk-pk) @1e−9 (Notes 1, 2)
− 0.2 UI
t
CKJIT
Clock Period Jitter (RMS) (Note 2)
− 50 ps
t
CYCJIT
Clock Cycle-to-Cycle Jitter (RMS) (Note 2)
− 100 ps
t
R
Rise Time (20−80%) (Note 3)
150 ps 0.25 UI
t
F
Fall Time (20−80%) (Note 3)
150 ps 0.25 UI
DCYC
Clock Duty Cycle (Note 2)
45 55 %
t
CHSKEW
Mean Clock to Data Skew (Notes 1, 4)
−0.1 0.1 UI
t
PHYSKEW
PHY-to-PHY Skew (Notes 1, 5)
− 2.1 UI
t
DIFFSKEW
Mean Differential Skew (Note 6)
−100 100 ps
1. One UI is defined as the normalized mean time between one edge and the following edge of the clock.
2. Taken from the 0 V crossing point with the DLL off.
3. Also defined with a maximum loading capacitance of 10 pF on any pin. The loading capacitance may also need to be less for higher bitrates
so the rise and fall times do not exceed the maximum 0.3 UI.
4. The absolute mean skew between the Clock lane and any Data Lane in the same PHY between any edges.
5. The absolute skew between any Clock in one PHY and any Data lane in any other PHY between any edges.
6. Differential skew is defined as the skew between complementary outputs. It is measured as the absolute time between the two
complementary edges at mean VCM point. Note that differential skew also is related to the DVCM_AC spec which also must not be exceeded.
HiVCM Electrical Specifications
The HiSPi 2.0 specification also defines an alternative
signaling level mode called HiVCM. Both V
OD
and V
CM
are
still scalable with V
DD
_HiSPi_TX, but with
V
DD
_HiSPi_TX nominal set to 1.8 V the common-mode is
elevated to around 0.9 V.
Table 21. HiVCM POWER SUPPLY AND OPERATING TEMPERATURES
Symbol
Parameter Min Typ Max Unit
I
DD
_HiSPi_TX
HiVCM Current Consumption (Notes 1, 2)
− − n * 34 mA
I
DD
_HiSPi
HiSPi PHY Current Consumption (Notes 1, 2, 3)
− − n * 45 mA
T
J
Operating Temperature (Note 4)
−30 − 70 °C
1. Where ‘n’ is the number of PHYs.
2. Temperature of 25°C.
3. Up to 700 Mbps.
4. Specification values may be exceeded when outside this temperature range.
AR0330CM
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17
Table 22. HiVCM ELECTRICAL VOLTAGE AND IMPEDANCE SPECIFICATION (T
J
= 25°C)
Symbol
Parameter Min Typ Max Unit
V
CM
HiVCM DC Mean Common Mode Voltage
0.76 0.90 1.07 V
|V
OD
|
HiVCM DC Mean Differential Output Voltage
200 280 350 mV
DV
CM
Change in V
CM
between Logic 1 and 0
− − 25 mV
|V
OD
|
Change in |V
OD
| between Logic 1 and 0
− − 25 mV
NM
V
OD
Noise Margin
− − ±30 %
|DV
CM
|
Difference in V
CM
between any Two Channels
− − 50 mV
|DV
OD
|
Difference in V
OD
between any Two Channels
− − 100 mV
DV
CM_AC
Common-mode AC Voltage (pk) without V
CM
Cap
Termination
− − 50 mV
DV
CM_AC
Common-mode AC Voltage (pk) with V
CM
Cap
Termination
− − 30 mV
V
OD_AC
Maximum Overshoot Peak |V
OD
|
− − 1.3 * |V
OD
| V
V
Diff_pk-pk
Maximum Overshoot V
Diff
pk-pk
− − 2.6 * V
OD
V
R
O
Single-ended Output Impedance
40 70 100
W
DR
O
Output Impedance Mismatch
− − 20 %
Table 23. HiVCM ELECTRICAL AC SPECIFICATION
Symbol
Parameter Min Max Unit
1/UI
Data Rate (Note 1)
280 700 Mbps
t
PW
Bitrate Period (Note 1)
1.43 3.57 ns
t
PRE
Max Setup Time from Transmitter (Notes 1, 2)
0.3 − UI
t
POST
Max Gold Time from Transmitter (Notes 1, 2)
0.3 − UI
t
EYE
Eye Width (Notes 1, 2)
− 0.6 UI
t
TOTALJIT
Data Total Jitter (pk-pk) @1e−9 (Notes 1, 2)
− 0.2 UI
t
CKJIT
Clock Period Jitter (RMS) (Note 2)
− 50 ps
t
CYCJIT
Clock Cycle-to-Cycle Jitter (RMS) (Note 2)
− 100 ps
t
R
Rise Time (20−80%) (Note 3)
150 ps 0.3 UI
t
F
Fall Time (20−80%) (Note 3)
150 ps 0.3 UI
D
CYC
Clock Duty Cycle (Note 2)
45 55 %
t
CHSKEW
Clock to Data Skew (Notes 1, 4)
−0.1 0.1 UI
t
PHYSKEW
PHY-to-PHY Skew (Notes 1, 5)
− 2.1 UI
t
DIFFSKEW
Mean Differential Skew (Note 6)
−100 100 ps
1. One UI is defined as the normalized mean time between one edge and the following edge of the clock.
2. Taken from the 0 V crossing point with the DLL off.
3. Also defined with a maximum loading capacitance of 10 pF on any pin. The loading capacitance may also need to be less for higher bitrates
so the rise and fall times do not exceed the maximum 0.3 UI.
4. The absolute mean skew between the Clock lane and any Data Lane in the same PHY between any edges.
5. The absolute mean skew between any Clock in one PHY and any Data lane in any other PHY between any edges.
6. Differential skew is defined as the skew between complementary outputs. It is measured as the absolute time between the two
complementary edges at mean V
CM
point. Note that differential skew also is related to the DVCM_AC spec which also must not be exceeded.
AR0330CM
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18
Electrical Definitions
Figure 10 is the diagram defining differential amplitude
V
OD
, V
CM,
and rise and fall times. To measure V
OD
and
V
CM
use the DC test circuit shown in Figure 11 and set the
HiSPi PHY to constant Logic 1 and Logic 0. Measure V
oa
,
V
ob
and V
CM
with voltmeters for both Logic 1 and Logic 0.
Figure 10. Single-Ended and Differential Signals
V
oa
V
ob
V
OD
V
OD_AC
V
CM
+
V
oa
) V
ob
2
80%
20%
t
F
t
R
0 V
V
Diff
V
diff_pkpk
V
OD
=
|V
oa
− V
ob
|
V
OD
=
|V
ob
− V
oa
|
Differential Signal
Single-Ended Signals
Figure 11. DC Test Circuit
V
oa
V
ob
V
CM
V
V
50 W
50 W
V
OD
(m) +
Ť
V
oa
(m) * V
ob
(m)
Ť
(eq. 1)
Where m is either “1” for logic 1 or “0” for logic 0.
V
OD
+
V
OD
(1) ) V
OD
(0)
2
(eq. 2)
V
Diff
+ V
OD
(1) ) V
OD
(0)
(eq. 3)
DV
OD
+
Ť
V
OD
(1) * V
OD
(0)
Ť
(eq. 4)
V
CM
+
V
CM
(1) ) V
CM
(0)
2
(eq. 5)
DV
CM
+
Ť
V
CM
(1) * V
CM
(0)
Ť
(eq. 6)
Both V
OD
and V
CM
are measured for all output channels.
The worst case
DV
OD
is defined as the largest difference in
V
OD
between all channels regardless of logic level. And the
worst case
DV
CM
is similarly defined as the largest
difference in V
CM
between all channels regardless of logic
level.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P53

AR0330CM1C00SHAAH3-GEVB

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Manufacturer:
ON Semiconductor
Description:
Optical Sensor Development Tools 3.5 MP 1/3" CIS HB
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