EPCQ256SI16N Datasheet EPCQ512ASI16N, EPCQ32SI8N, EPCQ128SI16N | P16-P18

1.4.6. Address Range for EPCQ512/A

Table 13. Address Range for Sectors 1023..0 and Subsectors 16383..0 in EPCQ512/A

Devices

Sector Subsector Address Range (Byte Addresses in HEX)

Start End

1023 16383

3FFF000 3FFFFFF

. .

16368

3FF0000 3FF0FFF

. .

511 8191

1FFF000 1FFFFFF

. .

8176

FF0000 1FF0FFF

. .

255 4095

FFF000 FFFFFF

. .

4080

FF0000 FF0FFF

. .

127 2047

7FF000 7FFFFF

. .

2032

7F0000 7F0FFF

. .

63 1023

3FF000 3FFFFF

. .

1008

3F0000 3F0FFF

. .

0 15

F000 FFFF

. .

H'0000000 H'0000FFF

1.5. Memory Operations

This section describes the operations that you can use to access the memory in EPCQ

devices. When performing the operation, addresses and data are shifted in and out of

the device serially, with the MSB first.

1. Quad-Serial Configuration (EPCQ) Devices Datasheet

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Quad-Serial Configuration (EPCQ) Devices Datasheet

1.5.1. Timing Requirements

When the active low chip select (nCS) signal is driven low, shift in the operation code

into the EPCQ device using the serial data (DATA) pin. Each operation code bit is

latched into the EPCQ device on the rising edge of the DCLK.

While executing an operation, shift in the desired operation code, followed by the

address or data bytes. See related information for more information about the address

and data bytes. The device must drive the nCS pin high after the last bit of the

operation sequence is shifted in.

For read operations, the data read is shifted out on the DATA pin. You can drive the

nCS pin high when any bit of the data is shifted out.

For write and erase operations, drive the nCS pin high at a byte boundary, that is in a

multiple of eight clock pulses. Otherwise, the operation is rejected and not executed.

All attempts to access the memory contents while a write or erase cycle is in progress

are rejected, and the write or erase cycle continues unaffected.

1.5.2. Addressing Mode

The 3-byte addressing mode is enabled by default. To access the EPCQ256 or

EPCQ512/A memory, you must use the 4-byte addressing mode. In 4-byte addressing

mode, the address width is 32-bit address. To enable the 4-byte addressing mode, you

must execute the 4BYTEADDREN operation. This addressing mode takes effect

immediately after you execute the 4BYTEADDREN operation and remains active in the

subsequent power-ups. To disable the 4-byte addressing mode, you must execute the

4BYTEADDREX operation.

Note: If you are using the Intel Quartus Prime software or the SRunner software to program

the EPCQ256 or EPCQ512/A device, you do not need to execute the 4BYTEADDREN

operation. The Intel Quartus Prime software enables the 4-byte addressing mode

when programming the device automatically.

1.6. Registers

1.6.1. Status Register

1. Quad-Serial Configuration (EPCQ) Devices Datasheet

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Quad-Serial Configuration (EPCQ) Devices Datasheet

Table 14. Status Register Bits

Bit R/W Default

Value

Name Value Description

7 R/W 0 None

6 R/W 0 BP3 (Block

Protect Bit)

(9)

(10)

Table 15 on page 19 through Table 26 on page

24 list the protected area with reference to

the block protect bits.

Determine the area of

the memory protected

from being written or

erased unintentionally.

5 R/W 0 TB (Top/Bottom

Bit)

• 1=Protected area starts from the bottom of

the memory array.

• 0=Protected area starts from the top of the

memory array.

Determine that the

protected area starts

from the top or

bottom of the memory

array.

4 R/W 0 BP2

(9)

Table 15 on page 19 through Table 26 on page

24 list the protected area with reference to

the block protect bits.

Determine the area of

the memory protected

from being written or

erased unintentionally.

3 BP1

(9)

2 BP0

(9)

1 R 0 WEL (Write

Enable Latch

Bit)

• 1=Allows the following operation to run:

— Write Bytes

— Write Status Register

— Erase Bulk

— Erase Die

— Erase Sector

• 0=Rejects the above mentioned operations.

Allows or rejects

certain operation to

run.

0 R 0 WIP (Write in

Progress Bit)

• 1=One of the following operation is in

progress:

— Write Status Register

— Write NVCR

— Write Bytes

— Erase

• 0=no write or erase cycle in progress

Indicates if there is a

command in progress.

1.6.1.1. Read Status Register Operation (05h)

Figure 1. Read Status Operation Timing Diagram

nCS

DCLK

DATA0

DATA

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

7 6 5 4 3 2 1 0 7 2 1 0 76 5 4 3

Operation Code (05h)

MSB MSB

Status Register Out Status Register Out

High Impedance

(9)

The erase bulk and erase die operation is only available when all the block protect bits are set

to 0. When any of the block protect bits are set to 1, the relevant area is protected from being

written by a write bytes operation or erased by an erase sector operation.

(10)

Applicable for EPCQ64, EPCQ128, EPCQ256, and EPCQ512/A devices only.

1. Quad-Serial Configuration (EPCQ) Devices Datasheet

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Quad-Serial Configuration (EPCQ) Devices Datasheet

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EPCQ256SI16N

Mfr. #:

Buy EPCQ256SI16N

Manufacturer:

Intel / Altera

Description:

FPGA - Configuration Memory IC - Ser. Config Mem Flash 256Mb 50 MHz

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EPCQ256SI16N

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