Status Register Content Memory Content
TB Bit BP3 Bit BP2 Bit BP1 Bit BP0 Bit Protected Area Unprotected Area
0 1 1 0 1 All sectors None
0 1 1 1 0 All sectors None
0 1 1 1 1 All sectors None
1.6.1.1.6. Block Protection Bits in EPCQ64 when TB Bit is Set to 1
Table 20. Block Protection Bits in EPCQ64 when TB Bit is Set to 1
Status Register Content Memory Content
TB Bit BP3 Bit BP2 Bit BP1 Bit BP0 Bit Protected Area Unprotected Area
1 0 0 0 0 None All sectors
1 0 0 0 1 Sector 0 Sectors (1 to 127)
1 0 0 1 0 Sectors (0 to 1) Sectors (2 to 127)
1 0 0 1 1 Sectors (0 to 3) Sectors (4 to 127)
1 0 1 0 0 Sectors (0 to 7) Sectors (8 to 127)
1 0 1 0 1 Sectors (0 to 15) Sectors (16 to 127)
1 0 1 1 0 Sectors (0 to 31) Sectors (32 to 127)
1 0 1 1 1 Sectors (0 to 63) Sectors (64 to 127)
1 1 0 0 0 All sectors None
1 1 0 0 1 All sectors None
1 1 0 1 0 All sectors None
1 1 0 1 1 All sectors None
1 1 1 0 0 All sectors None
1 1 1 0 1 All sectors None
1 1 1 1 0 All sectors None
1 1 1 1 1 All sectors None
1.6.1.1.7. Block Protection Bits in EPCQ128 when TB Bit is Set to 0
Table 21. Block Protection Bits in EPCQ128 when TB Bit is Set to 0
Status Register Content Memory Content
TB Bit BP3 Bit BP2 Bit BP1 Bit BP0 Bit Protected Area Unprotected Area
0 0 0 0 0 None All sectors
0 0 0 0 1 Sector 255 Sectors (0 to 254)
0 0 0 1 0 Sectors (254 to 255) Sectors (0 to 253)
0 0 0 1 1 Sectors (252 to 255) Sectors (0 to 251)
0 0 1 0 0 Sectors (248 to 255) Sectors (0 to 247)
0 0 1 0 1 Sectors (240 to 255) Sectors (0 to 239)
continued...
1. Quad-Serial Configuration (EPCQ) Devices Datasheet
CF52012 | 2018.06.01
Quad-Serial Configuration (EPCQ) Devices Datasheet
21
