Pin
Nam
e
AS x1 Pin-Out
Diagram
AS x4 Pin-Out
Diagram
Pin Type Description
Pin
Number
in 8-Pin
SOIC
Package
Pin
Number
in 16-
Pin SOIC
Package
Pin
Number
in 8-Pin
SOIC
Package
Pin
Number
in 16-
Pin SOIC
Package
that serially transfers data out of the EPCQ device to the
FPGA. The data is shifted out on the falling edge of the DCLK
signal.
DAT
A1
2 8 2 8 I/O For AS x1 and x4 modes, use this pin as an output signal pin
that serially transfers data out of the EPCQ device to the
FPGA during read or configuration operations. The transition
of the signal is on the falling edge of the DCLK signal.
During the extended dual input fast write bytes or extended
quad input fast write bytes operation, this pin acts as an
input signal pin that serially transfers data into the EPCQ
device. The data is latched on the rising edge of the DCLK
signal.
During extended dual input fast read or extended quad input
fast read operations, this pin acts as an output signal pin
that serially transfer data out of the EPCQ device to the
FPGA. The data is shifted out on the falling edge of the DCLK
signal. During read, configuration, or program operations,
you can enable the EPCQ device by pulling the nCS signal
low.
DAT
A2
— — 3 9 I/O For AS x1 mode, extended dual input fast write bytes
operation and extended dual input fast read operation, this
pin must connect to a 3.3-V power supply.
For AS x4 mode, use this pin as an output signal that serially
transfers data out of the EPCQ device to the FPGA during
read or configuration operations. The transition of the signal
is on the falling edge of the DCLK signal.
During the extended quad input fast write bytes operation,
this pin acts as an input pin that serially transfers data into
the EPCQ device. The data is latched on the rising edge of
the DCLK signal. During the extended quad input fast read
operation, this pin acts as an output signal pin that serially
transfers data out of the EPCQ device to the FPGA. The data
is shifted out on the falling edge of the DCLK signal.
DAT
A3
— — 7 1 I/O For AS x1 mode, extended dual input fast write bytes
operation and extended dual input fast read operation, this
pin must connect to a 3.3-V power supply.
For AS x4 mode, use this pin as an output signal that serially
transfers data out of the EPCQ device to the FPGA during
read or configuration operations. The transition of the signal
is on the falling edge of the DCLK signal.
During the extended quad input fast write bytes operation,
this pin acts as an input pin that serially transfers data into
the EPCQ device. The data is latched on the rising edge of
the DCLK signal. During the extended quad input fast read
operation, this pin acts as an output signal pin that serially
transfers data out of the EPCQ device to the FPGA. The data
is shifted out on the falling edge of the DCLK signal.
nCS
1 7 1 7 Input
The active low nCS input signal toggles at the beginning and
end of a valid operation. When this signal is high, the device
is deselected and the DATA pin is tri-stated. When this signal
is low, the device is enabled and is in active mode. After
power up, the EPCQ device requires a falling edge on the
nCS signal before you begin any operation.
continued...
1. Quad-Serial Configuration (EPCQ) Devices Datasheet
CF52012 | 2018.06.01
Quad-Serial Configuration (EPCQ) Devices Datasheet
45
