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EPCQ256SI16N

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48
Figure 7. 4BYTEADDREX Timing Diagram
Operation Code (E9h)
3 4 5 6 710 2
nCS
DCLK
DATA0
Related Information
Write Enable Operation (06h) on page 31
1.7.2. Write Enable Operation (06h)
When you enable the write enable operation, the write enable latch bit is set to 1 in
the status register. You must execute this operation before the write bytes, write
status, erase bulk, erase sector, extended dual input fast write bytes, extended quad
input fast write bytes, 4BYTEADDREN, and 4BYTEADDREX operations.
Figure 8. Write Enable Operation Timing Diagram
nCS
DCLK
DATA0
DATA[3:1]
Operation Code (06h)
High Impedance
0 1 2 3 4 5 6 7
1.7.3. Write Disable Operation (04h)
The write disable operation resets the write enable latch bit in the status register. To
prevent the memory from being written unintentionally, the write enable latch bit is
automatically reset when implementing the write disable operation, and under the
following conditions:
• Power up
• Write bytes operation completion
• Write status operation completion
• Erase bulk operation completion
• Erase sector operation completion
• Extended dual input fast write bytes operation completion
• Extended quad input fast write bytes operation completion
1. Quad-Serial Configuration (EPCQ) Devices Datasheet
CF52012 | 2018.06.01
Quad-Serial Configuration (EPCQ) Devices Datasheet
31
Figure 9. Write Disable Operation Timing Diagram
Operation Code (04h)
DATA0
nCS
DCLK
DATA[3:1]
High Impedance
0
1
2
3
4
5
6
7
1.7.4. Read Bytes Operation (03h)
When you execute the read bytes operation, you first shift in the read bytes operation
code, followed by a 3-byte addressing mode (A[23..0]) or a 4-byte addressing mode
(A[31..0]). Each address bit must be latched in on the rising edge of the DCLK
signal. After the address is latched in, the memory contents of the specified address
are shifted out serially on the DATA1 pin, beginning with the MSB. For reading Raw
Programming Data File (.rpd), the content is shifted out serially beginning with the
LSB. Each data bit is shifted out on the falling edge of the DCLK signal. The maximum
DCLK frequency during the read bytes operation is 50 MHz.
Figure 10. Read Bytes Operation Timing Diagram
To access the entire EPCQ256 or EPCQ512/A memory, use 4-byte addressing mode. In the 4-byte addressing
mode, the address width is 32-bit address.
nCS
DCLK
DATA0
DATA1
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
Operation Code (03h) 24-Bit Address
23 22 21 3 2 1 0
7 76 5 4 3 2 1 0
MSB
MSB
High Impedance
DATA Out 1 DATA Out 2
The first byte address can be at any location. The device automatically increases the
address to the next higher address after shifting out each byte of data. Therefore, the
device can read the whole memory with a single read bytes operation. When the
device reaches the highest address, the address counter restarts at 0x000000,
allowing the memory contents to be read out indefinitely until the read bytes
operation is terminated by driving the nCS signal high. If the read bytes operation is
shifted in while a write or erase cycle is in progress, the operation is not executed and
does not affect the write or erase cycle in progress.
Related Information
Write Operation Timing on page 40
The Write Operation Parameters provides more information about t
WS
, t
ES
and t
WB
.
1. Quad-Serial Configuration (EPCQ) Devices Datasheet
CF52012 | 2018.06.01
Quad-Serial Configuration (EPCQ) Devices Datasheet
32
1.7.5. Fast Read Operation (0Bh)
When you execute the fast read operation, you first shift in the fast read operation
code, followed by a 3-byte addressing mode (A[23..0]) or a 4-byte addressing
mode (A[31..0]), and dummy clock cycle(s) with each bit being latched-in during
the rising edge of the DCLK signal. Then, the memory contents at that address is
shifted out on DATA1 with each bit being shifted out at a maximum frequency of
100 MHz during the falling edge of the DCLK signal.
Figure 11. Fast Read Operation Timing Diagram
To access the entire EPCQ256 or EPCQ512/A memory, use 4-byte addressing mode. In the 4-byte addressing
mode, the address width is 32-bit address.
nCS
DCLK
DATA0
DATA1
nCS
DCLK
DATA0
DATA1
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
Operation Code (0Bh)
8 Dummy Clock Cycles
24-Bit Address
MSB
MSB MSB MSB
High Impedance
23 22 21 3 2 1 0
Byte1 Byte 2
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
7 6 5 4 3 2 1 0
The first byte address can be at any location. The device automatically increases the
address to the next higher address after shifting out each byte of data. Therefore, the
device can read the whole memory with a single fast read operation. When the device
reaches the highest address, the address counter restarts at 0x000000, allowing the
read sequence to continue indefinitely.
You can terminate the fast read operation by driving the nCS signal high at any time
during data output. If the fast read operation is shifted in while an erase, program, or
write cycle is in progress, the operation is not executed and does not affect the erase,
program, or write cycle in progress.
1.7.6. Extended Dual Input Fast Read Operation (BBh)
This operation is similar to the fast read operation except that the data and addresses
are shifted in and out on the DATA0 and DATA1 pins.
1. Quad-Serial Configuration (EPCQ) Devices Datasheet
CF52012 | 2018.06.01
Quad-Serial Configuration (EPCQ) Devices Datasheet
33
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48

EPCQ256SI16N

Mfr. #:
Buy EPCQ256SI16N
Manufacturer:
Intel / Altera
Description:
FPGA - Configuration Memory IC - Ser. Config Mem Flash 256Mb 50 MHz
Lifecycle:
New from this manufacturer.
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