The device initiates a self-timed erase sector cycle immediately after the nCS signal is
driven high. For details about the self-timed erase sector cycle time, refer to t
ES
in the
related information below. You must account for this amount of delay before another
page of memory is written. Alternatively, you can check the write in progress bit in the
status register by executing the read status operation while the self-timed erase cycle
is in progress. The write in progress bit is set to 1 during the self-timed erase cycle
and 0 when it is complete. The write enable latch bit in the status register is set to 0
before the self-timed erase cycle is complete.
Related Information
Write Operation Timing on page 40
The Write Operation Parameters provides more information about t
WS
, t
ES
and t
WB
.
1.7.14. Erase Subsector Operation
The erase subsector operation allows you to erase a certain subsector in the EPCQ
device by setting all the bits inside the subsector to 1 or 0xFF. This operation is useful
if you want to access the unused subsectors as a general purpose memory in your
applications. You must execute the write enable operation before the erase subsector
operation.
When you execute the erase subsector operation, you must first shift in the erase
subsector operation code, followed by the 3-byte addressing mode (A[23..0]) or the
4-byte addressing mode (A[31..0]) of the chosen subsector on the DATA0 pin. The
3-byte addressing mode or the 4-byte addressing mode for the erase subsector
operation can be any address inside the specified subsector. For details about the
subsector address range, refer to the related information below. Drive the nCS signal
high after the eighth bit of the erase subsector operation code has been latched in.
Figure 21. Erase Subsector Operation Timing Diagram
To access the entire EPCQ256 or EPCQ512/A memory, use 4-byte addressing mode. In the 4-byte addressing
mode, the address width is 32-bit address.
DATA0
Operation Code (20h) 24-Bit Address
nCS
DCLK
0 1 2 3 4 5 6 7 8 9 28 29 30 31
3 2
1 023 22
MSB
The device initiates a self-timed erase subsector cycle immediately after the nCS
signal is driven high. For details about the self-timed erase subsector cycle time, refer
to related the information below. You must account for this amount of delay before
another page of memory is written. Alternatively, you can check the write in progress
bit in the status register by executing the read status operation while the self-timed
erase cycle is in progress. The write in progress bit is set to 1 during the self-timed
erase cycle and 0 when it is complete. The write enable latch bit in the status register
is set to 0 before the self-timed erase cycle is complete.
Related Information
• Write Operation Timing on page 40
1. Quad-Serial Configuration (EPCQ) Devices Datasheet
CF52012 | 2018.06.01
Quad-Serial Configuration (EPCQ) Devices Datasheet
39
