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EPCQ256SI16N

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48
Figure 12. Extended Dual Input Fast Read Operation Timing Diagram
To access the entire EPCQ256 or EPCQ512/A memory, use 4-byte addressing mode. In the 4-byte addressing
mode, the address width is 32-bit address.
10 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
22 20 18 16 14 12 10 8 6 4 2 0
23 21 19 17 15 13 11 9 7 5 3 1
6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6
7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7
2827 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
Operation Code (BBh)
Dummy Clock Cycles
Byte 1 Byte 2 Byte 3 Byte 4
nCS
DCLK
DATA0
DATA1
nCS
DCLK
DATA0
DATA1
24-Bit Address
I/O switches from Input to Output
1.7.7. Extended Quad Input Fast Read Operation (EBh)
This operation is similar to the extended dual input fast read operation except that the
data and addresses are shifted in and out on the DATA0, DATA1, DATA2, and DATA3
pins.
Figure 13. Extended Quad Input Fast Read Operation
To access the entire EPCQ256 or EPCQ512/A memory, use 4-byte addressing mode. In the 4-byte addressing
mode, the address width is 32-bit address.
2
11 12
13
14
0
DATA0
DCLK
Operating Code (EBh)
15 16
20
17
18
19
4 0
20 16 12 8
4
22
21
23
5 1
21 17 13 9
DATA1
High Impedance
Byte 1
5
7
7 3
23 19 15 11
6
6 2
22 18 14 10
DATA2
High Impedance
High Impedance
Byte 2
6 Dummy Clock Cycles
24 Bit Address
DATA3
I/O Switches from Input to Output
1 3
64
5
7
10
8
9
4 0
4
0
5
1
5
1
6 2
6
2
7 3
7
3
nCS
1.7.8. Read Device Identification Operation (9Fh)
This operation reads the 8-bit device identification of the EPCQ device from the DATA1
output pin. If this operation is shifted in while an erase or write cycle is in progress,
the operation is not executed and does not affect the erase or write cycle in progress.
1. Quad-Serial Configuration (EPCQ) Devices Datasheet
CF52012 | 2018.06.01
Quad-Serial Configuration (EPCQ) Devices Datasheet
34
Table 32. EPCQ Device Identification
EPCQ Device Silicon ID (Binary Value)
EPCQ16 b'0001 0101
EPCQ32 b'0001 0110
EPCQ64 b'0001 0111
EPCQ128 b'0001 1000
EPCQ256 b'0001 1001
EPCQ512/A b'0010 0000
The 8-bit device identification of the EPCQ device is shifted out on the DATA1 pin on
the falling edge of the DCLK signal.
Figure 14. Read Device Identification Operation Timing Diagram
nCS
DCLK
DATA0
DATA1
0 1 2 3 4 5 6 7 8 9 10 20 21 23 24 25 26 27 28 29 30 31 32
Operation Code (9Fh)
Two Dummy Bytes
15
14 13
3 2 1 0
7 6 5 4 3 2 1 0
MSB
MSB
High Impedance
Device ID
Don’t Care
1.7.9. Write Bytes Operation (02h)
This operation allows bytes to be written to the memory. You must execute the write
enable operation before the write bytes operation. After the write bytes operation is
completed, the write enable latch bit in the status register is set to 0.
When you execute the write bytes operation, you shift in the write bytes operation
code, followed by a 3-byte addressing mode (A[23..0]) or a 4-byte addressing mode
(A[31..0]), and at least one data byte on the DATA0 pin. If the eight LSBs
(A[7..0]) are not all 0, all sent data that goes beyond the end of the current page is
not written into the next page. Instead, this data is written at the start address of the
same page. You must ensure the nCS signal is set low during the entire write bytes
operation.
Figure 15. Write Bytes Operation Timing Diagram
To access the entire EPCQ256 or EPCQ512/A memory, use 4-byte addressing mode. In the 4-byte addressing
mode, the address width is 32-bit address.
DATA0
Operation Code (02h)
24-Bit Address Data Byte 1 Data Byte 2 Data Byte 256
0
1
2
3
4
5
6
7
8
9
10
28
29
30
31
32
nCS
DCLK
33
34
35
36
37 38
39
40
41
42 43
44
45
46
47
3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 023 22 21 7 6 5 4 3 2 1 0
2072
2073
2074 2075
2076
2077
2078
2079
MSB MSB MSB MSB
If more than 256 data bytes are shifted into the EPCQ device with a write bytes
operation, the previously latched data is discarded and the last 256 bytes are written
to the page. However, if less than 256 data bytes are shifted into the EPCQ device,
they are guaranteed to be written at the specified addresses and the other bytes of
the same page are not affected.
1. Quad-Serial Configuration (EPCQ) Devices Datasheet
CF52012 | 2018.06.01
Quad-Serial Configuration (EPCQ) Devices Datasheet
35
The device initiates a self-timed write cycle immediately after the nCS signal is driven
high. For details about the self-timed write cycle time, refer to t
WB
in the related
information below. You must account for this amount of delay before another page of
memory is written. Alternatively, you can check the write in progress bit in the status
register by executing the read status operation while the self-timed write cycle is in
progress. The write in progress bit is set to 1 during the self-timed write cycle and 0
when it is complete.
Note: You must erase all the memory bytes of EPCQ devices before you implement the write
bytes operation. You can erase all the memory bytes by executing the erase sector
operation in a sector or the erase bulk operation throughout the entire memory
1.7.10. Extended Dual Input Fast Write Bytes Operation (D2h)
This operation is similar to the write bytes operation except that the data and
addresses are shifted in on the DATA0 and DATA1 pins.
Figure 16. Extended Dual Input Fast Write Bytes Timing Diagram
To access the entire EPCQ256 or EPCQ512/A memory, use 4-byte addressing mode. In the 4-byte addressing
mode, the address width is 32-bit address.
21 3 9 10
11 12
13
14
0
14 12 10 8
DCLK
DATA0
nCS
DATA1
Operation Code (D2h)
DCLK
DATA0
nCS
DATA1
33
21 22 23 24 25 26 27 28 29 30 31 32
1 7 5 1
3
7 5 1
0
4 02
15 16
17
18
19
20
23 21 19 17 15 13 11 9 7 1
22 20 18 16 6 0
24-bit Address
34
MSB
35
0
7
1
MSB
MSB
MSB
Data In 4
Data In 1 Data In 3
Data In 2
6 4 02
1
MSB
Data In 256
18 19 20
24
5 3
4 5
6
7 8
5
3
7 5
3
3
6 4 2
6 4 2
6 4 2
0
6
7 5 3
1.7.11. Extended Quad Input Fast Write Bytes Operation (12h or 38h)
This operation is similar to the extended dual input fast write bytes operation except
that the data and addresses are shifted in on the DATA0, DATA1, DATA2, and DATA3
pins.
1. Quad-Serial Configuration (EPCQ) Devices Datasheet
CF52012 | 2018.06.01
Quad-Serial Configuration (EPCQ) Devices Datasheet
36
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48

EPCQ256SI16N

Mfr. #:
Buy EPCQ256SI16N
Manufacturer:
Intel / Altera
Description:
FPGA - Configuration Memory IC - Ser. Config Mem Flash 256Mb 50 MHz
Lifecycle:
New from this manufacturer.
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