GS1531 Data Sheet
30573 - 7 February 2008 22 of 50
4. Detailed Description
4.1 Functional Overview
The GS1531 is a multi-rate serializer with an integrated cable driver. When used in
conjunction with the external GO1555/GO1525* Voltage Controlled Oscillator, a
transmit solution at 1.485Gb/s, 1.485/1.001Gb/s or 270Mb/s is realized.
The device has three different modes of operation which must be set through
external device pins.
When SMPTE mode is enabled, the device will accept 10-bit multiplexed or 20-bit
demultiplexed SMPTE compliant data at both HD and SD signal rates. The
device’s additional processing features are also enabled in this mode.
In DVB-ASI mode, the GS1531 will accept an 8-bit parallel DVB-ASI compliant
transport stream on its upper input bus. The serial output data stream will be
8b/10b encoded and stuffed.
The GS1531’s third mode allows for the serializing of data not conforming to
SMPTE or DVB-ASI streams.
The provided serial digital outputs feature a high impedance mode, output mute on
loss of parallel clock and adjustable signal swing. The output slew rate is
automatically controlled by the SD/HD
setting.
In the digital signal processing core, several data processing functions are
implemented including SMPTE 352M and EDH data packet generation and
insertion, and automatic video standards detection. These features are all enabled
by default, but may be individually disabled via internal registers accessible
through the GSPI host interface.
Finally, the GS1531 contains a JTAG interface for boundary scan test
implementations.
*For new designs use GO1555
4.2 Parallel Data Inputs
Data inputs enter the device on the rising edge of PCLK as shown in Figure 4-1.
The input data format is defined by the setting of the external SD/HD
,
SMPTE_BYPASS
and DVB_ASI pins and may be presented in 10-bit or 20-bit
format. The input data bus width is controlled independently from the internal data
bus width by the 20bit/10bit
input pin.
GS1531 Data Sheet
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Figure 4-1: PCLK to Data Timing
4.2.1 Parallel Input in SMPTE Mode
When the device is operating in SMPTE mode, see SMPTE Mode on page 25, both
SD and HD data may be presented to the input bus in either multiplexed or
demultiplexed form depending on the setting of the 20bit/10bit
input pin.
In 20-bit mode, (20bit/10bit
= HIGH), the input data format should be word aligned,
demultiplexed luma and chroma data. Luma words should be presented to
DIN[19:10] while chroma words should occupy DIN[9:0].
In 10-bit mode, (20bit/10bit
= LOW), the input data format should be word aligned,
multiplexed luma and chroma data. The data should be presented to DIN[19:10].
DIN[9:0] will be high impedance in this mode.
4.2.2 Parallel Input in DVB-ASI Mode
When operating in DVB-ASI mode, see DVB-ASI mode on page 26, the GS1531
requires the input data bus to be configured for 10-bit operation (20bit/10bit
=
LOW).
The device accepts 8-bit data words on DIN[17:10] such that DIN17 = HIN is the
most significant bit of the encoded transport stream data and DIN10 = AIN is the
least significant bit.
In addition, DIN19 and DIN18 are configured as the DVB-ASI control signals
INSSYNCIN and KIN respectively. See DVB-ASI mode on page 26 for a
description of these DVB-ASI specific input signals.
The pins DIN[9:0] are high impedance when the GS1531 is operating in DVB-ASI
mode.
4.2.3 Parallel Input in Data-Through Mode
When operating in Data-Through mode, see Data-Through Mode on page 28, the
GS1531 passes data presented to the parallel input bus to the serial output without
performing any encoding or scrambling.
The input data bus width accepted by the device in this mode is controlled by the
setting of the 20bit/10bit
pin.
PCLK
DIN[19:0]
DATA
Control signal
input
tSU
tIH
GS1531 Data Sheet
30573 - 7 February 2008 24 of 50
4.2.4 Parallel Input Clock (PCLK)
The frequency of the PCLK input signal required by the GS1531 is determined by
the input data format. Table 4-1 below lists the possible input signal formats and
their corresponding parallel clock rates.
NOTE: DVB-ASI input requires a 10-bit wide input data bus (20bit/10bit
= LOW).
Table 4-1: Parallel Data Input Format
Input Data Format DIN
[19:10]
DIN [9:0] PCLK
Control Signals
20bit/
10bit
SD/
HD
SMPTE_BYPASS DVB_ASI
SMPTE MODE
20bit DEMULTIPLEXED SD LUMA CHROMA 13.5MHz HIGH HIGH HIGH LOW
10bit MULTIPLEXED SD LUMA /
CHROMA
HIGH
IMPEDANCE
27MHz LOW HIGH HIGH LOW
20bit DEMULTIPLEXED HD LUMA CHROMA 74.25 or
74.25/
1.001MHz
HIGH LOW HIGH LOW
10bit MULTIPLEXED HD LUMA /
CHROMA
HIGH
IMPEDANCE
148.5 or
148.5/
1.001MHz
LOW LOW HIGH LOW
DVB-ASI MODE
10bit DVB-ASI DVB-ASI
DATA
HIGH
IMPEDANCE
27MHz LOW HIGH LOW HIGH
LOW HIGH LOW HIGH
DATA-THROUGH MODE
20bit DEMULTIPLEXED SD DATA DATA 13.5MHz HIGH HIGH LOW LOW
10bit MULTIPLEXED SD DATA HIGH
IMPEDANCE
27MHz LOW HIGH LOW LOW
20bit DEMULTIPLEXED HD DATA DATA 74.25 or
74.25/
1.001MHz
HIGH LOW LOW LOW
10bit MULTIPLEXED HD DATA HIGH
IMPEDANCE
148.5 or
148.5/
1.001MHz
LOW LOW LOW LOW

GS1531-CBE2

Mfr. #:
Manufacturer:
Semtech
Description:
Video ICs BGA-100 Pin
Lifecycle:
New from this manufacturer.
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