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GS1531-CBE2

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P50
GS1531 Data Sheet
30573 - 7 February 2008 37 of 50
4.6.3.4 Ancillary Data Checksum Generation and Insertion
The GS1531 will calculate checksums for all detected ancillary data packets
presented to the device. These calculated checksum values are inserted into the
data stream prior to serialization.
Ancillary data checksum generation and insertion will only take place if the
ANC_CSUM_INS bit of the IOPROC_DISABLE register is set LOW.
4.6.3.5 Line Based CRC Generation and Insertion
The GS1531 will generate and insert line based CRC words into both the Y and C
channels of the data stream. This feature is only available in HD mode and is
enabled by setting the CRC_INS bit of the IOPROC_DISABLE register LOW.
4.6.3.6 HD Line Number Generation and Insertion
In HD mode, the GS1531 will calculate and insert line numbers into the Y and C
channels of the output data stream.
Line number generation is in accordance with the relevant HD video standard as
determined by the device, see Automatic Video Standard Detection on page 28.
This feature is enabled when SD/HD
= LOW, and the LNUM_INS bit of the
IOPROC_DISABLE register is set LOW.
4.6.3.7 TRS Generation and Insertion
The GS1531 can generate and insert 10-bit TRS code words into the data stream
as required. This feature is enabled by setting the TRS_INS bit of the
IOPROC_DISABLE register LOW.
TRS word generation will be performed in accordance with the timing parameters
generated by the flywheel which will be locked either to the received TRS ID words
or the supplied H, V, and F timing signals, see Internal Flywheel on page 25.
4.7 Parallel-To-Serial Conversion
The parallel data output of the internal data processing blocks is fed to the
parallel-to-serial converter. The function of this block is to generate a serial data
stream from the 10-bit or 20-bit parallel data words and pass the stream to the
integrated cable driver.
GS1531 Data Sheet
30573 - 7 February 2008 38 of 50
4.8 Serial Digital Data PLL
To obtain a clean clock signal for serialization and transmission, the input PCLK is
locked to an external reference signal via the GS1531's integrated phase-locked
loop. This high quality analog PLL allows the GS1531 to significantly attenuate jitter
on the incoming PCLK. This PLL is also responsible for generating all internal clock
signals required by the device.
Internal division ratios for the locked PCLK are determined by the setting of the
SD/HD
and 20bit/10bit pins as shown in Table 4-10.
4.8.1 External VCO
The GS1531 requires the GO1555/GO1525* external voltage controlled oscillator
as part of its internal PLL.
Power for the external VCO is generated entirely by the GS1531 from an integrated
voltage regulator. The internal regulator uses +3.3V supplied on the CP_VDD /
CP_GND pins to provide +2.5V on the VCO_VCC / VCO_GND pins.
The external VCO produces a 1.485GHz reference signal for the PLL, input on the
VCO pin of the device. Both reference and control signals should be referenced to
the supplied VCO_GND as shown in the recommended application circuit of
Typical Application Circuit on page 46.
*For new designs use GO1555
4.8.2 Lock Detect Output
The lock detect block controls the serial digital output signal and indicates the lock
status of the device via the LOCKED output pin.
LOCKED will be asserted HIGH if and only if the internal data PLL has locked the
PCLK signal to the external VCO reference signal and one of the following is true:
1. The device is set to operate in SMPTE mode and has detected SMPTE TRS
words in the serial stream; or
2. The device is set to operate in DVB-ASI mode and has detected K28.5 sync
characters in the serial stream; or
Table 4-10: Serial Digital Output Rates
Supplied PCLK Rate Serial Digital
Output Rate
Pin Settings
SD/HD 20bit/10bit
74.25 or
74.25/1.001 MHz
1.485 or
1.485/1.001Gb/s
LOW HIGH
148.5 or
148.5/1.001MHz
1.485 or
1.485/1.001Gb/s
LOW LOW
13.5MHz 270Mb/s HIGH HIGH
27MHz 270Mb/s HIGH LOW
GS1531 Data Sheet
30573 - 7 February 2008 39 of 50
3. The device is set to operate in Data-Through mode.
4.8.3 Loop Bandwidth Adjustment
For new designs the GO1555 is recommended for use with the GS1531. The
recommended loop bandwidth control component values are listed in Table 4-11
and can be seen in Section 5.1 Typical Application Circuit.
Designs using the GO1525 VCO will require different loop bandwidth control
components. The component values are listed in Table 4-11.
NOTE: When using the GS1531 with the GS4911B clock generator a narrower
loop bandwidth for the GS1531 serializer should be used. For more details please
refer to Section 2.5 of the GS4911B Reference Design.
4.9 Serial Digital Output
The GS1531 contains an integrated current mode differential serial digital cable
driver with automatic slew rate control.
The integrated cable driver uses a separate power supply of +1.8V DC supplied via
the CD_VDD and CD_GND pins.
To enable the output, SDO_EN/DIS
must be set HIGH. Setting the SDO_EN/DIS
signal LOW will cause the SDO and SDO
output pins to become high impedance,
resulting in reduced device power consumption.
Gennum recommends using the GS1528A SDI Dual Slew-Rate Cable Driver to
meet SMPTE specifications.
4.9.1 Output Swing
Nominally, the voltage swing of the serial digital output is 800mVp-p single-ended
into a 75Ω load. This is set externally by connecting the RSET pin to CD_VDD
through 281Ω .
The output swing may be decreased by increasing the value of the RSET resistor.
The relationship is approximated by the curve shown in Figure 4-4.
Alternatively, the serial digital output swing can drive 800mVp-p into a 50Ω load.
Since the output swing is reduced by a factor of approximately one third when the
smaller load is used, the RSET resistor must be 187Ω to obtain 800mVp-p.
Table 4-11: GO1555 Loop Bandwidth Adjustment
Component GO1555 GO1525
LB_CONT 100nF 100nF
R
LF-CP_CAP
33Ω 50Ω
CP_CAP 47nF 22nF
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P50

GS1531-CBE2

Mfr. #:
Buy GS1531-CBE2
Manufacturer:
Semtech
Description:
Video ICs BGA-100 Pin
Lifecycle:
New from this manufacturer.
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