GS1531 Data Sheet
30573 - 7 February 2008 40 of 50
Figure 4-4: Serial Digital Output Swing
4.9.2 Serial Digital Output Mute
The GS1531 will automatically mute the serial digital output when the LOCKED
output signal is LOW. In this case, the SDO and SDO
signals are set to a constant
voltage level.
4.10 GSPI Host Interface
The GSPI, or Gennum Serial Peripheral Interface, is a 4-wire interface provided to
allow the host to enable additional features of the device and /or to provide
additional status information through configuration registers in the GS1531.
The GSPI comprises a serial data input signal SDIN, serial data output signal
SDOUT, an active low chip select CS
, and a burst clock SCLK. The burst clock
must have a duty cycle between 40% and 60%.
Because these pins are shared with the JTAG interface port, an additional control
signal pin JTAG/HOST
is provided. When JTAG/HOST is LOW, the GSPI interface
is enabled.
When operating in GSPI mode, the SCLK, SDIN, and CS
signals are provided by
the host interface. The SDOUT pin is a high-impedance output allowing multiple
devices to be connected in parallel and selected via the CS
input. The interface is
illustrated in the Figure 4-5 below.
All read or write access to the GS1531 is initiated and terminated by the host
processor. Each access always begins with a 16-bit command word on SDIN
indicating the address of the register of interest. This is followed by a 16-bit data
word on SDIN in write mode, or a 16-bit data word on SDOUT in read mode.
50Ω load
300
400
500
600
700
800
900
1000
250
300
350
400
450
500
550
600
650
700
RSET(Ω)
ΔV
SDO
(mVp-p)
200
75Ω load
GS1531 Data Sheet
30573 - 7 February 2008 41 of 50
Figure 4-5: Gennum Serial Peripheral Interface (GSPI)
4.10.1 Command Word Description
The command word is transmitted MSB first and contains a read/write bit, nine
reserved bits and a 6-bit register address. Set R/W = '1' to read and R/W = '0' to
write from the GSPI.
Command words are clocked into the GS1531 on the rising edge of the serial clock
SCLK. The appropriate chip select signal, CS
, must be asserted low a minimum of
1.5ns (t0 in Figure 4-8 and Figure 4-9) before the first clock edge to ensure proper
operation.
Each command word must be followed by only one data word to ensure proper
operation.
SCLK
CS
SDOUT
SDIN
SCLK
CS
SDIN
SDOUT
Application Host
GS1531
GS1531 Data Sheet
30573 - 7 February 2008 42 of 50
Figure 4-6: Command Word
Figure 4-7: Data Word
4.10.2 Data Read and Write Timing
Read and write mode timing for the GSPI interface is shown in Figure 4-8 and
Figure 4-9 respectively. The maximum SCLK frequency allowed is 6.6MHz.
When writing to the registers via the GSPI, the MSB of the data word may be
presented to SDIN immediately following the falling edge of the LSB of the
command word. All SDIN data is sampled on the rising edge of SCLK.
When reading from the registers via the GSPI, the MSB of the data word will be
available on SDOUT 12ns (t5) following the falling edge of the LSB of the command
word, and thus may be read by the host on the very next rising edge of the clock.
The remaining bits are clocked out by the GS1531 on the negative edges of SCLK.
Figure 4-8: GSPI Read Mode Timing
Figure 4-9: GSPI Write Mode Timing
R/W RSV RSV RSV A0A1A2A3A4A5RSVRSVRSVRSVRSV RSV
MSB
LSB
D15 D14 D13 D12 D0D1D2
D3D4
D5
D6D7
D8
D9
D11 D10
MSB
LSB
SDOUT
R/W
RSV
RSV
A0A1
A2A3
A4
A5
RSV
RSV
RSV
RSV
RSVRSV
D15 D14 D13 D12
D0
D1
D2
D3
D4D5
D6
D7
D8
D9
D11
D10
SCLK
CS
SDIN
RSV
t0
t2
t3
input data
setup time
duty
cycle
t4
period
t5
t6
output data
hold time
R/W
RSV
RSV
A0A1
A2A3
A4
A5
RSV
RSV
RSV
RSV
RSVRSV
D15 D14 D13 D12
D0
D1
D2
D3
D4D5
D6
D7
D8
D9
D11
D10
SCLK
CS
SDIN
RSV
t0
t2
t3
input data
setup time
duty
cycle
t4
period

GS1531-CBE2

Mfr. #:
Manufacturer:
Semtech
Description:
Video ICs BGA-100 Pin
Lifecycle:
New from this manufacturer.
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