GS1531 Data Sheet
30573 - 7 February 2008 43 of 50
4.10.3 Configuration and Status Registers
Table 4-12 summarizes the GS1531's internal status and configuration registers.
All of these registers are available to the host via the GSPI and are all individually
addressable.
Where status registers contain less than the full 16 bits of information however, two
or more registers may be combined at a single logical address.
4.11 JTAG
When the JTAG/HOST input pin of the GS1531 is set HIGH, the host interface port
will be configured for JTAG test operation. In this mode, pins H4 to H6 and J6
become TMS, TCK, TDO, and TDI. In addition, the RESET_TRST
pin will operate
as the test reset pin.
Boundary scan testing using the JTAG interface will be enabled in this mode.
There are two methods in which JTAG can be used on the GS1531:
1. As a stand-alone JTAG interface to be used at in-circuit ATE (Automatic Test
Equipment) during PCB assembly; or
2. Under control of the host for applications such as system power on self tests.
When the JTAG tests are applied by ATE, care must be taken to disable any other
devices driving the digital I/O pins. If the tests are to be applied only at ATE, this
can be accomplished with tri-state buffers used in conjunction with the
JTAG/HOST
input signal. This is shown in Figure 4-10.
Table 4-12: GS1531 Internal Registers
Address Register Name See Section
000h IOPROC_DISABLE Section 4.6.3
002h EDH_FLAG Section 4.6.3.3
004h VIDEO_STANDARD Section 4.6.2
00Ah - 00Bh VIDEO_FORMAT Section 4.6.3.1
00Eh - 011h RASTER_STRUCTURE Section 4.6.2
012h - 019h EDH_CALC_RANGES Section 4.6.3.3
01Bh - 01Ch LINE_352M Section 4.6.3.1
