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GS1531-CBE2

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P50
GS1531 Data Sheet
30573 - 7 February 2008 31 of 50
These features are only available when the device is set to operated in SMPTE
mode and the IOPROC_EN/DIS
pin is set HIGH. Individual insertion features may
be enabled or disabled via the IOPROC_DISABLE register (Table 4-5).
All of the IOPROC_DISABLE register bits default to '0' after device reset, enabling
all of the processing features. To disable any individual error correction feature, the
host interface must set the corresponding bit HIGH in this register.
Table 4-5: Host Interface Description for Internal Processing Disable Register
Register Name Bit Name Description R/W Default
IOPROC_DISABLE
Address: 000h
15-9 – Not Used. – –
8 H_CONFIG Horizontal sync timing input configuration. Set LOW
when the H input timing is based on active line
blanking (default). Set HIGH when the H input
timing is based on the H bit of the TRS words. See
Figure 4-2.
R/W 0
7 – Not Used. – –
6 352M_INS SMPTE352M packet insertion. In HD mode, 352M
packets are inserted in the Y channel only when one
of the bytes in the VIDEO_FORMAT_A or
VIDEO_FORMAT_B registers are programmed with
non-zero values. The IOPROC_EN/DIS pin and
SMPTE_BYPASS
pin must also be set HIGH. Set
HIGH to disable.
R/W 0
5 ILLEGAL_REMAP Illegal Code Remapping. Detection and correction
of illegal code words within the active picture area
(AP). The IOPROC_EN/DIS
pin and
SMPTE_BYPASS
pin must also be set HIGH. Set
HIGH to disable.
R/W 0
4 EDH_CRC_INS Error Detection & Handling (EDH) Cyclical
Redundancy Check (CRC) error correction. In SD
mode the GS1531 will generate and insert EDH
packets. The IOPROC_EN/DIS
pin and
SMPTE_BYPASS
pin must also be set HIGH. Set
HIGH to disable.
R/W 0
3 ANC_CSUM_INS Ancillary Data Checksum insertion. The
IOPROC_EN/DIS
pin and SMPTE_BYPASS pin
must also be set HIGH. Set HIGH to disable.
R/W 0
2 CRC_INS Y and C line-based CRC insertion. In HD mode,
line-based CRC words are inserted in both the Y
and C channels. The IOPROC_EN/DIS
pin and
SMPTE_BYPASS
pin must be also set HIGH. Set
HIGH to disable
R/W 0
1 LNUM_INS Y and C line number insertion - HD mode only. The
IOPROC_EN/DIS
pin and SMPTE_BYPASS pin
must be set HIGH. Set HIGH to disable.
R/W 0
0 TRS_INS Timing Reference Signal Insertion. Occurs only
when IOPROC_EN/DIS
is HIGH and
SMPTE_BYPASS
is HIGH. Set HIGH to disable.
R/W 0
GS1531 Data Sheet
30573 - 7 February 2008 32 of 50
4.6.3.1 SMPTE 352M Payload Identifier Insertion
The GS1531 can generate and insert SMPTE 352M payload identifier ancillary
data packets into the data stream, based on information programmed into the host
interface.
When this feature is enabled, the device will automatically generate the ancillary
data preambles, (DID, SDID, DBN, DC), and calculate the checksum. The SMPTE
352M packet will be inserted into the data stream according to the line numbers
programmed in the LINE_352M registers (Table 4-6).
The insertion process will only take place if one or more of the four
VIDEO_FORMAT registers (Table 4-7) have been programmed with non-zero
values. In addition, the GS1531 requires the 352M_INS bit of the
IOPROC_DISABLE register be set LOW.
NOTE 1: For the purpose of determining the line and pixel position for insertion, the
GS1531 will differentiate between PsF and interlaced formats by interrogating bits
14 and 15 of the VIDEO_FORMAT_A register.
The packets will be inserted immediately after the EAV word in SD video streams
and immediately after the line-based CRC word in the Y channel of HD video
streams.
NOTE 2: It is the responsibility of the user to ensure that there is sufficient space
in the horizontal blanking interval for the insertion of the SMPTE 352M packets.
If there are other ancillary data packets present, the SMPTE 352M packet will be
inserted in the first available location in the horizontal ancillary space. Ancillary
data must be adjacent to the EAV in SD streams or to the line based-CRC in HD
streams. Where there is insufficient space available, the 352M packets will not be
inserted.
Table 4-6: Host Interface Description for SMPTE 352M Packet Line Number Insertion Registers
Register Name Bit Name Description R/W Default
LINE_352M_f1
Address: 01Bh
15-11 – Not Used. – –
10-0 LINE_0_352M[10:0] Line number where SMPTE352M packet is inserted
in field 1.
R/W 0
LINE_352M_f2
Address: 01Ch
15-11 – Not Used. – –
10-0 LINE_1_352M[10:0] Line number where SMPTE352M packet is inserted
in field 2.
R/W 0
GS1531 Data Sheet
30573 - 7 February 2008 33 of 50
4.6.3.2 Illegal Code Remapping
If the ILLEGAL_REMAP bit of the IOPROC_DISABLE register is set LOW, the
GS1531 will remap all codes within the active picture between the values of 3FCh
and 3FFh to 3FBh. All codes within the active picture area between the values of
000h and 003h will be remapped to 004h.
In addition, 8-bit TRS and ancillary data preambles will be remapped to 10-bit
values if this feature is enabled.
4.6.3.3 EDH Generation and Insertion
When operating in SD mode, (SD/HD
= HIGH), the GS1531 will generate and
insert complete EDH packets into the data stream. Packet generation and insertion
will only take place if the EDH_CRC_INS bit of the IOPROC_DISABLE register is
set LOW.
The GS1531 will generate all of the required EDH packet data including all ancillary
data preambles, (DID, DBN, DC), reserved code words and checksum. Calculation
of both full field (FF) and active picture (AP) CRC's will be carried out by the device.
SMPTE RP165 specifies the calculation ranges and scope of EDH data for
standard 525 and 625 component digital interfaces. The GS1531 will utilize these
standard ranges by default.
If the received video format does not correspond to 525 or 625 digital component
video standards as determined by the flywheel pixel and line counters, then one of
two schemes for determining the EDH calculation ranges will be employed:
1. Ranges will be based on the line and pixel ranges programmed by the host
interface; or
2. In the absence of user-programmed calculation ranges, ranges will be
determined from the received TRS ID words or supplied H, V, and F timing
signals, see Internal Flywheel on page 25.
Table 4-7: Host Interface Description for SMPTE 352M Payload Identifier Registers
Register Name Bit Name Description R/W Default
VIDEO_FORMAT_B
Address: 00Bh
15-8 SMPTE352M
Byte 4
SMPTE 352M Byte 4 information must be
programmed in this register when 352M_INS =
LOW.
R/W 0
7-0 SMPTE352M
Byte 3
SMPTE 352M Byte 3 information must be
programmed in this register when 352M_INS =
LOW.
R/W 0
VIDEO_FORMAT_A
Address: 00Ah
15-8 SMPTE352M
Byte 2
SMPTE 352M Byte 2 information must be
programmed in this register when 352M_INS =
LOW.
R/W 0
7-0 SMPTE 352M
Byte 1
SMPTE 352M Byte 1 information must be
programmed in this register when 352M_INS =
LOW.
R/W 0
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P50

GS1531-CBE2

Mfr. #:
Buy GS1531-CBE2
Manufacturer:
Semtech
Description:
Video ICs BGA-100 Pin
Lifecycle:
New from this manufacturer.
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