OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

LPC1225FBD48/321,1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P61
LPC122X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 26 August 2011 19 of 61
NXP Semiconductors
LPC122x
32-bit ARM Cortex-M0 microcontroller
• Supports memory-to-memory, memory-to-peripheral, and peripheral-to-memory
transfers.
• Supports multiple DMA cycle types and multiple DMA transfer widths.
• Performs all DMA transfers using the single AHB-Lite burst type.
7.8 CRC engine
The Cyclic Redundancy Check (CRC) engine with programmable polynomial settings
supports several CRC standards commonly used. To save system power and bus
bandwidth, the CRC engine supports DMA transfers.
7.8.1 Features
• Supports three common polynomials CRC-CCITT, CRC-16, and CRC-32.
– CRC-CCITT: x
16
+ x
12
+ x
5
+ 1
– CRC-16: x
16
+ x
15
+ x
2
+ 1
– CRC-32: x
32
+ x
26
+ x
23
+ x
22
+ x
16
+ x
12
+ x
11
+ x
10
+ x
8
+ x
7
+ x
5
+ x
4
+ x
2
+ x + 1
• Bit order reverse and 1’s complement programmable setting for input data and CRC
sum.
• Programmable seed number setting.
• Supports CPU programmed I/O or DMA back-to-back transfer.
• Accept any size of data width per write: 8, 16 or 32-bit.
– 8-bit write: 1-cycle operation
– 16-bit write: 2-cycle operation (8-bit 2-cycle)
– 32-bit write: 4-cycle operation (8-bit 4-cycle)
7.9 Fast general purpose parallel I/O
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate
registers allow setting or clearing any number of outputs simultaneously. The value of the
output register may be read back as well as the current state of the port pins.
7.9.1 Features
• Bit level set and clear registers allow a single instruction to set or clear any number of
bits in one port.
• Direction control of individual bits.
• All I/O default to inputs after reset.
7.10 UARTs
The LPC122x contains two UARTs. UART0 supports full modem control and RS-485/9-bit
mode and allows both software address detection and automatic hardware address
detection using 9-bit mode.
The UARTs include a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
LPC122X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 26 August 2011 20 of 61
NXP Semiconductors
LPC122x
32-bit ARM Cortex-M0 microcontroller
7.10.1 Features
• 16-byte Receive and Transmit FIFOs.
• Register locations conform to 16C550 industry standard.
• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
• Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
• Auto-baud capabilities and FIFO control mechanism that enables software flow
control implementation.
• Support for RS-485/9-bit mode (UART0).
• Support for modem control (UART0).
7.11 SSP/SPI serial I/O controller
The LPC122x contain one SSP/SPI controller. The SSP/SPI controller is capable of
operation on a SSP, 4-wire SSI, or Microwire bus. It can interact with multiple masters and
slaves on the bus. Only a single master and a single slave can communicate on the bus
during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits
to 16 bits of data flowing from the master to the slave and from the slave to the master. In
practice, often only one of these data flows carries meaningful data.
7.11.1 Features
• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses
• Synchronous serial communication
• Master or slave operation
• 8-frame FIFOs for both transmit and receive
• 4-bit to 16-bit frame
7.12 I
2
C-bus serial I/O controller
The LPC122x contain one I
2
C-bus controller.
The I
2
C-bus is bidirectional for inter-IC control using only two wires: a serial clock line
(SCL) and a serial data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I
2
C is a multi-master bus and can be
controlled by more than one bus master connected to it.
7.12.1 Features
• The I
2
C-interface is a standard I
2
C-compliant bus interface with open-drain pins and
supports I
2
C Fast-mode Plus with bit rates of up to 1 Mbit/s.
• Programmable digital glitch filter providing a 60 ns to 1 s input filter.
• Easy to configure as master, slave, or master/slave.
• Programmable clocks allow versatile rate control.
LPC122X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 26 August 2011 21 of 61
NXP Semiconductors
LPC122x
32-bit ARM Cortex-M0 microcontroller
• Bidirectional data transfer between masters and slaves.
• Multi-master bus (no central master).
• Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
• The I
2
C-bus can be used for test and diagnostic purposes.
• The I
2
C-bus controller supports multiple address recognition and a bus monitor mode.
7.13 10-bit ADC
The LPC122x contains one ADC. It is a single 10-bit successive approximation ADC with
eight channels.
7.13.1 Features
• 10-bit successive approximation ADC.
• Input multiplexing among 8 pins.
• Power-down mode.
• Measurement range 0 V to V
DD(3V3)
.
• 10-bit conversion time of 257 kHz.
• Burst conversion mode for single or multiple inputs.
• Optional conversion on transition of input pin or counter/timer match signal.
• Individual result registers for each ADC channel to reduce interrupt overhead.
7.14 Comparator block
The comparator block consists of two analog comparators.
7.14.1 Features
• Up to six selectable external sources per comparator; fully configurable on either
positive or negative comparator input channels.
• BOD 0.9 V internal reference voltage selectable on both comparators; configurable on
either positive or negative comparator input channels.
• 32-stage voltage ladder internal reference voltage selectable on both comparators;
configurable on either positive or negative comparator input channels.
• Voltage ladder source voltage is selectable from an external pin or an internal 3.3 V
voltage rail if external power source is not available.
• Voltage ladder can be separately powered down for applications only requiring the
comparator function.
• Relaxation oscillator circuitry output for a feedback 555-style timer application.
• Common interrupt connected to NVIC.
• Comparator outputs selectable as synchronous or asynchronous.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P61

LPC1225FBD48/321,1

Mfr. #:
Buy LPC1225FBD48/321,1
Manufacturer:
NXP Semiconductors
Description:
ARM Microcontrollers - MCU CORTEX M0 80K FL 8K DMA CRC ADC COMPARTR
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet