LPC122X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 26 August 2011 34 of 61
NXP Semiconductors
LPC122x
32-bit ARM Cortex-M0 microcontroller
10.1 Peripheral power consumption
The supply current per peripheral is measured as the difference in supply current between
the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG
and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both
registers and no code is executed. Measured on a typical sample at T
amb
=25 C and
V
DD(3V3)
= 3.3 V.
10.2 Power consumption
Power measurements in Active, Sleep, and Deep-sleep modes were performed under the
following conditions (see LPC122x user manual):
Active mode: all GPIO pins set to input with external pull-up resistors.
Sleep and Deep-sleep modes: all GPIO pins set to output driving LOW.
Deep power-down mode: all GPIO pins set to input with external pull-up resistors.
Table 8. Peripheral power consumption
Peripheral Typical current consumption I
DD
in mA
Frequency
independent
24 MHz 12 MHz
system
oscillator + PLL
IRC + PLL system
oscillator
IRC
IRC 0.29 - - - -
PLL (PLL output
frequency = 24 MHz)
1.87 - - - -
WDosc (WDosc output
frequency = 500 kHz)
0.25 - - - -
BOD 0.06 - - - -
Analog comparator 0/1 - 0.05 0.05 0.03 0.02
ADC - 1.86 1.85 1.61 1.61
CRC engine - 0.04 0.04 0.02 0.02
16-bit timer 0 (CT16B0) - 0.09 0.09 0.04 0.04
16-bit timer 1 (CT16B1) - 0.09 0.09 0.04 0.04
32-bit timer 0 (CT32B0) - 0.08 0.08 0.04 0.04
32-bit timer 1 (CT32B1) - 0.08 0.08 0.04 0.04
GPIO0 - 0.34 0.34 0.17 0.17
GPIO1 - 0.34 0.34 0.17 0.17
GPIO2 - 0.36 0.37 0.18 0.18
I2C - 0.09 0.09 0.05 0.05
IOCON - 0.09 0.10 0.05 0.05
RTC - 0.10 0.10 0.05 0.05
SSP - 0.30 0.29 0.15 0.15
UART0 - 0.52 0.51 0.26 0.26
UART1 - 0.52 0.51 0.26 0.26
DMA - 0.18 0.18 0.09 0.09
WWDT - 0.06 0.06 0.03 0.03
LPC122X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 26 August 2011 35 of 61
NXP Semiconductors
LPC122x
32-bit ARM Cortex-M0 microcontroller
Conditions: T
amb
= 25 C; active mode entered executing code
while(1){}
from flash; all
peripherals disabled in the SYSAHBCLKCTRL register; all peripheral clocks disabled; internal
pull-up resistors disabled; BOD disabled.
(1) System oscillator and system PLL disabled; IRC enabled.
(2) System oscillator and system PLL enabled; IRC disabled.
(3) System oscillator enabled; IRC and system PLL disabled.
Fig 6. Active mode: Typical supply current I
DD
versus supply voltage V
DD(3V3)
for
different system clock frequencies (all peripherals disabled)
Conditions: V
DD(3V3)
= 3.3 V; active mode entered executing code
while(1){}
from flash; all
peripherals disabled in the SYSAHBCLKCTRL register; all peripheral clocks disabled; internal
pull-up resistors disabled; BOD disabled.
(1) System oscillator and system PLL disabled; IRC enabled.
(2) System oscillator and system PLL enabled; IRC disabled.
(3) System oscillator enabled; IRC and system PLL disabled.
Fig 7. Active mode: Typical supply current I
DD
versus temperature for different system
clock frequencies (peripherals disabled)
LPC122X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 26 August 2011 36 of 61
NXP Semiconductors
LPC122x
32-bit ARM Cortex-M0 microcontroller
Conditions: T
amb
= 25 C; active mode entered executing code
while(1){}
from flash; all
peripherals enabled in the SYSAHBCLKCTRL register.
(1) System oscillator and system PLL disabled; IRC enabled.
(2) System oscillator and system PLL enabled; IRC disabled.
(3) System oscillator enabled with external clock input; IRC and system PLL disabled.
Fig 8. Active mode: Typical supply current I
DD
versus supply voltage V
DD(3V3)
for
different system clock frequencies (all peripherals enabled)
Conditions: V
DD(3V3)
= 3.3 V; active mode entered executing code
while(1){}
from flash; all
peripherals enabled in the SYSAHBCLKCTRL register.
(1) System oscillator and system PLL disabled; IRC enabled.
(2) System oscillator and system PLL enabled; IRC disabled.
(3) System oscillator enabled with external clock input; IRC and system PLL disabled.
Fig 9. Active mode: Typical supply current I
DD
versus temperature for different system
clock frequencies (peripherals enabled)

LPC1225FBD48/321,1

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
ARM Microcontrollers - MCU CORTEX M0 80K FL 8K DMA CRC ADC COMPARTR
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