OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

LPC1225FBD48/321,1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P61
LPC122X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 26 August 2011 7 of 61
NXP Semiconductors
LPC122x
32-bit ARM Cortex-M0 microcontroller
(1) High-current output driver.
Remark: For a full listing of all functions for each pin see Table 3
.
Fig 3. Pin configuration LQFP48 package
LPC122x
XTALIN R/PIO1_0
XTALOUT R/PIO0_31
VREF_CMP R/PIO0_30
PIO0_19 PIO0_18
PIO0_20 PIO0_17
PIO0_21 PIO0_16
PIO0_22 PIO0_15
PIO0_23 PIO0_14
PIO0_24 RESET/PIO0_13
SWDIO/PIO0_25 PIO0_12
(1)
SWCLK/PIO0_26 PIO0_11
PIO0_27
(1)
PIO0_10
PIO0_28
(1)
V
SSIO
PIO0_29
(1)
V
DD(IO)
PIO0_0 RTCXIN
PIO0_1 RTCXOUT
PIO0_2 V
DD(3V3)
PIO0_3 V
SS
PIO0_4 PIO1_6
PIO0_5 PIO1_5
PIO0_6 PIO1_4
PIO0_7 PIO1_3/WAKEUP
PIO0_8
PIO0_9
PIO1_2
R/PIO1_1
002aaf724
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
13
14
15
16
17
18
19
20
21
22
23
48
47
46
45
44
43
42
41
40
39
38
37
24
LPC122X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 26 August 2011 8 of 61
NXP Semiconductors
LPC122x
32-bit ARM Cortex-M0 microcontroller
6.2 Pin description
All pins except the supply pins can have more than one function as shown in Table 3. The
pin function is selected through the pin’s IOCON register in the IOCONFIG block. The
multiplexed functions (see Table 4
) include the counter/timer inputs and outputs, the
UART receive, transmit, and control functions, and the serial wire debug functions.
For each pin, the default function is listed first together with the pin’s reset state.
Table 3. LPC122x pin description
Symbol
Pin LQFP48
Pin LQFP64
Start
logic
input
Type Reset
state
[1]
Description
PIO0_0 to PIO0_31 I/O Port 0 — Port 0 is a 32-bit I/O port with individual direction and
function controls for each bit. The operation of port 0 pins
depends on the function selected through the IOCONFIG
register block.
PIO0_0/RTS0
15 19
[2]
[3]
yes I/O I; PU PIO0_0 — General purpose digital input/output pin.
O- RTS0
— Request To Send output for UART0.
PIO0_1/RXD0/
CT32B0_CAP0/
CT32B0_MAT0
16 20
[2]
[3]
yes I/O I; PU PIO0_1 — General purpose digital input/output pin.
I- RXD0 — Receiver input for UART0.
I- CT32B0_CAP0 — Capture input, channel 0 for 32-bit timer 0.
O- CT32B0_MAT0 — Match output, channel 0 for 32-bit timer 0.
PIO0_2/TXD0/
CT32B0_CAP1/
CT32B0_MAT1
17 21
[2]
[3]
yes I/O I; PU PIO0_2 — General purpose digital input/output pin.
O- TXD0 — Transmitter output for UART0.
I- CT32B0_CAP1 — Capture input, channel 1 for 32-bit timer 0.
O- CT32B0_MAT1 — Match output, channel 1 for 32-bit timer 0.
PIO0_3/DTR0
/
CT32B0_CAP2/
CT32B0_MAT2
18 22
[2]
[3]
yes I/O I; PU PIO0_3 — General purpose digital input/output pin.
O- DTR0
— Data Terminal Ready output for UART0.
I- CT32B0_CAP2 — Capture input, channel 2 for 32-bit timer 0.
O- CT32B0_MAT2 — Match output, channel 2 for 32-bit timer 0.
PIO0_4/DSR0
/
CT32B0_CAP3/
CT32B0_MAT3
19 23
[2]
[3]
yes I/O I; PU PIO0_4 — General purpose digital input/output pin.
I- DSR0
— Data Set Ready input for UART0.
I- CT32B0_CAP3 — Capture input, channel 3 for 32-bit timer 0.
O- CT32B0_MAT3 — Match output, channel 3 for 32-bit timer 0.
PIO0_5/DCD0
20 24
[2]
[3]
yes I/O I; PU PIO0_5 — General purpose digital input/output pin.
I- DCD0
— Data Carrier Detect input for UART0.
PIO0_6/RI0
/
CT32B1_CAP0/
CT32B1_MAT0
21 25
[2]
[3]
yes I/O I; PU PIO0_6 — General purpose digital input/output pin.
I- RI0
— Ring Indicator input for UART0.
I- CT32B1_CAP0 — Capture input, channel 0 for 32-bit timer 1.
O- CT32B1_MAT0 — Match output, channel 0 for 32-bit timer 1.
LPC122X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 26 August 2011 9 of 61
NXP Semiconductors
LPC122x
32-bit ARM Cortex-M0 microcontroller
PIO0_7/CTS0/
CT32B1_CAP1/
CT32B1_MAT1
22 26
[2]
[3]
yes I/O I; PU PIO0_7 — General purpose digital input/output pin.
I- CTS0
— Clear To Send input for UART0.
I- CT32B1_CAP1 — Capture input, channel 1 for 32-bit timer 1.
O- CT32B1_MAT1 — Match output, channel 1 for 32-bit timer 1.
PIO0_8/RXD1/
CT32B1_CAP2/
CT32B1_MAT2
23 27
[2]
[3]
yes I/O I; PU PIO0_8 — General purpose digital input/output pin.
I- RXD1 — Receiver input for UART1.
I- CT32B1_CAP2 — Capture input, channel 2 for 32-bit timer 1.
O- CT32B1_MAT2 — Match output, channel 2 for 32-bit timer 1.
PIO0_9/TXD1/
CT32B1_CAP3/
CT32B1_MAT3
24 28
[2]
[3]
yes I/O I; PU PIO0_9 — General purpose digital input/output pin.
O- TXD1 — Transmitter output for UART1.
I- CT32B1_CAP3 — Capture input, channel 3 for 32-bit timer 1.
O- CT32B1_MAT3 — Match output, channel 3 for 32-bit timer 1.
PIO0_10/SCL 25 37
[4]
yes I/O I; IA PIO0_10 — General purpose digital input/output pin.
I/O - SCL — I
2
C-bus clock input/output.
PIO0_11/SDA/
CT16B0_CAP0/
CT16B0_MAT0
26 38
[4]
yes I/O I; IA PIO0_11 — General purpose digital input/output pin.
I/O - SDA — I
2
C-bus data input/output.
I- CT16B0_CAP0 — Capture input, channel 0 for 16-bit timer 0.
O- CT16B0_MAT0 — Match output, channel 0 for 16-bit timer 0.
PIO0_12/CLKOUT/
CT16B0_CAP1/
CT16B0_MAT1
27 39
[9]
no I/O I; PU PIO0_12 — General purpose digital input/output pin. A LOW
level on this pin during reset starts the ISP command handler.
High-current output driver.
O- CLKOUT — Clock out pin.
I- CT16B0_CAP1 — Capture input, channel 1 for 16-bit timer 0.
O- CT16B0_MAT1 — Match output, channel 1 for 16-bit timer 0.
RESET
/PIO0_13 28 40
[5]
[3]
no I I; PU RESET — External reset input: A LOW on this pin resets the
device, causing I/O ports and peripherals to take on their
default states, and processor execution to begin at address 0.
I/O - PIO0_13 — General purpose digital input/output pin.
PIO0_14/SCK 29 41
[2]
[3]
no I/O I; PU PIO0_14 — General purpose digital input/output pin.
I/O - SCK — Serial clock for SSP/SPI.
PIO0_15/SSEL/
CT16B1_CAP0/
CT16B1_MAT0
30 42
[2]
[3]
no I/O I; PU PIO0_15 — General purpose digital input/output pin.
I/O - SSEL — Slave select for SSP/SPI.
I- CT16B1_CAP0 — Capture input, channel 0 for 16-bit timer 1.
O- CT16B1_MAT0 — Match output, channel 0 for 16-bit timer 1.
PIO0_16/MISO/
CT16B1_CAP1/
CT16B1_MAT1
31 43
[2]
[3]
no I/O I; PU PIO0_16 — General purpose digital input/output pin.
I/O - MISO — Master In Slave Out for SSP/SPI.
I- CT16B1_CAP1 — Capture input, channel 1 for 16-bit timer 1.
O- CT16B1_MAT1 — Match output, channel 1 for 16-bit timer 1.
Table 3. LPC122x pin description
…continued
Symbol
Pin LQFP48
Pin LQFP64
Start
logic
input
Type Reset
state
[1]
Description
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P61

LPC1225FBD48/321,1

Mfr. #:
Buy LPC1225FBD48/321,1
Manufacturer:
NXP Semiconductors
Description:
ARM Microcontrollers - MCU CORTEX M0 80K FL 8K DMA CRC ADC COMPARTR
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet