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1. General description
The ADC1610S is a single-channel 16-bit Analog-to-Digital Converter (ADC) optimized for
high dynamic performance and low power consumption at sample rates up to 125 Msps.
Pipelined architecture and output error correction ensure the ADC1610S is accurate
enough to guarantee zero missing codes over the entire operating range. Supplied from a
single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode,
because of a separate digital output supply. It supports the Low Voltage Differential
Signaling (LVDS) Double Data Rate (DDR) output standard. An integrated Serial
Peripheral Interface (SPI) allows the user to easily configure the ADC. The device also
includes a programmable full-scale SPI to allow a flexible input voltage range from
1 V to 2 V (peak-to-peak). With excellent dynamic performance from the baseband to
input frequencies of 170 MHz or more, the ADC1610S is ideal for use in communications,
imaging and medical applications.
2. Features and benefits
3. Applications
ADC1610S series
Single 16-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps;
CMOS or LVDS DDR digital outputs
Rev. 04 — 2 July 2012 Product data sheet
SNR, 72.5 dBFS; SFDR, 88 dBc Input bandwidth, 600 MHz
Sample rate up to 125 Msps Power dissipation, 430 mW at 80 Msps
16-bit pipelined ADC core Serial Peripheral Interface (SPI)
Clock input divided by 2 for less jitter Duty cycle stabilizer
Single 3 V supply Fast OuT-of-Range (OTR) detection
Flexible input voltage range: 1 V (p-p) to
2 V (p-p)
Offset binary, two’s complement, gray
code
CMOS or LVDS DDR digital outputs Power-down and Sleep modes
HVQFN40 package
Wireless and wired broadband
communications
Portable instrumentation
Spectral analysis Imaging systems
Ultrasound equipment Software defined radio
ADC1610S_SER 4 © IDT 2012. All rights reserved.
Product data sheet Rev. 04 — 2 July 2012 2 of 38
Integrated Device Technology
ADC1610S series
Single 16-bit ADC; CMOS or LVDS DDR digital output
4. Ordering information
5. Block diagram
Table 1. Ordering information
Type number f
s
(Msps) Package
Name Description Version
ADC1610S125HN-C1 125 HVQFN40 plastic thermal enhanced very thin quad flat package; no
leads; 40 terminals; body 6 6 0.85 mm
SOT618-1
ADC1610S105HN-C1 105 HVQFN40 plastic thermal enhanced very thin quad flat package; no
leads; 40 terminals; body 6 6 0.85 mm
SOT618-1
ADC1610S080HN-C1 80 HVQFN40 plastic thermal enhanced very thin quad flat package; no
leads; 40 terminals; body 6 6 0.85 mm
SOT618-1
ADC1610S065HN-C1 65 HVQFN40 plastic thermal enhanced very thin quad flat package; no
leads; 40 terminals; body 6 6 0.85 mm
SOT618-1
Fig 1. Block diagram
ADC1610S
SPI INTERFACE
OUTPUT
DRIVERS
OUTPUT
DRIVERS
SYSTEM
REFERENCE AND
POWER
MANAGEMENT
ERROR
CORRECTION AND
DIGITAL
PROCESSING
ADC CORE
16-BIT
PIPELINED
T/H
INPUT
STAGE
INP
OTR
CS
SDIO/ODS
SCLK/DFS
PWD
REFT
CMOS:
D15 to D0
or
LVDS DDR:
D14_D15_M to D0_D1_M
D14_D15_P to D0_D1_P
INM
CLOCK INPUT
STAGE AND DUTY
CYCLE CONTROL
REFB
CLKMCLKP
SENSE
VREF
VCM
005aaa156
OE
CMOS:
DAV
or
LVDS DDR:
DAVP
DAVM
ADC1610S_SER 4 © IDT 2012. All rights reserved.
Product data sheet Rev. 04 — 2 July 2012 3 of 38
Integrated Device Technology
ADC1610S series
Single 16-bit ADC; CMOS or LVDS DDR digital output
6. Pinning information
6.1 Pinning
6.2 Pin description
Fig 2. Pin configuration with CMOS digital outputs
selected
Fig 3. Pin configuration with LVDS DDR digital
outputs selected
005aaa105
ADC1610S
HVQFN40
D11
AGND
VDDA
D10
INP D9
INM D8
AGND D7
VDDA D6
VCM D5
AGND D4
REFT D3
REFB D2
VDDA
CLKP
CLKM
DEC
OTR
D15
D14
D13
D12
VREF
SENSE
SDIO/DCS
SCLK/DFS
n.c.
DAV
VDDO
D0
D1
10 21
9 22
8 23
7 24
6 25
5 26
4 27
3 28
2 29
1 30
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
terminal 1
index area
Transparent top view
CS
PWD/OE
005aaa106
ADC1610S
HVQFN40
D10_D11_M
AGND
VDDA
D10_D11_P
INP D8_D9_M
INM D8_D9_P
AGND D6_D7_M
VDDA D6_D7_P
VCM D4_D5_M
AGND D4_D5_P
REFT D2_D3_M
REFB D2_D3_P
VDDA
CLKP
CLKM
DEC
OTR
D14_D15_M
D14_D15_P
D12_D13_M
D12_D13_P
VREF
SENSE
SDIO/DCS
SCLK/DFS
DAVP
DAVM
VDDO
D0_D1_P
D0_D1_M
10 21
9 22
8 23
7 24
6 25
5 26
4 27
3 28
2 29
1 30
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
terminal 1
index area
Transparent top view
CS
PWD/OE
Table 2. Pin description (CMOS digital outputs)
Symbol Pin Type
[1]
Description
REFB 1 O bottom reference
REFT 2 O top reference
AGND 3 G analog ground
VCM 4 O common-mode output voltage
VDDA 5 P analog power supply
AGND 6 G analog ground
INM 7 I complementary analog input
INP 8 I analog input
AGND 9 G analog ground
VDDA 10 P analog power supply
VDDA 11 P analog power supply
CLKP 12 I clock input
CLKM 13 I complementary clock input
DEC 14 O regulator decoupling node
PWD/OE
15 I power down, active HIGH; output enable, active LOW
OTR 16 O out of range

ADC1610S105HN/C1:5

Mfr. #:
Manufacturer:
Description:
IC ADC 16BIT PIPELINED 40HVQFN
Lifecycle:
New from this manufacturer.
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