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ADC1610S105HN/C1:5

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P38
ADC1610S_SER 4 © IDT 2012. All rights reserved.
Product data sheet Rev. 04 — 2 July 2012 31 of 38
Integrated Device Technology
ADC1610S series
Single 16-bit ADC; CMOS or LVDS DDR digital output
Table 20. Reset and operating mode control register (address 0005h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 SW_RST R/W reset digital section
0no reset
1 performs a reset of the SPI registers
6 to 4 RESERVED[2:0] 000 reserved
3 to 2 - 00 not used
1 to 0 OP_MODE[1:0] R/W operating mode
00 normal (power-up)
01 power-down
10 sleep
11 normal (power-up)
Table 21. Clock control register (address 0006h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 5 - 000 not used
4 SE_SEL R/W single-ended clock input pin select
0CLKM
1CLKP
3 DIFF_SE R/W differential/single-ended clock input select
0 fully differential
1 single-ended
2 - 0 not used
1 CLKDIV R/W clock input divide by 2
0disabled
1 enabled
0 DCS_EN R/W duty cycle stabilizer
0 disabled
1 enabled
ADC1610S_SER 4 © IDT 2012. All rights reserved.
Product data sheet Rev. 04 — 2 July 2012 32 of 38
Integrated Device Technology
ADC1610S series
Single 16-bit ADC; CMOS or LVDS DDR digital output
Table 22. Internal reference control register (address 0008h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 4 - 0 not used
3 INTREF_EN R/W programmable internal reference enable
0disable
1 active
2 to 0 INTREF[2:0] R/W programmable internal reference
000 FS = 2 V
001 FS = 1.78 V
010 FS = 1.59 V
011 FS = 1.42 V
100 FS = 1.26 V
101 FS = 1.12 V
110 FS = 1 V
111 reserved
Table 23. Output data standard control register (address 0011h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 5 - 000 not used
4 LVDS_CMOS R/W output data standard: LVDS DDR or CMOS
0CMOS
1 LVDS DDR
3 OUTBUF R/W output buffers enable
0output enabled
1 output disabled (high-Z)
2 OUTBUS_SWAP 0 outbus swapping
0 no swapping
1 output bus is swapping (MSB becomes LSB and vice
versa)
1 to 0 DATA_FORMAT[1:0] R/W output data format
00 offset binary
01 two’s complement
10 gray code
11 offset binary
ADC1610S_SER 4 © IDT 2012. All rights reserved.
Product data sheet Rev. 04 — 2 July 2012 33 of 38
Integrated Device Technology
ADC1610S series
Single 16-bit ADC; CMOS or LVDS DDR digital output
Table 24. Output clock register (address 0012h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 4 - 0000 not used
3 DAVINV R/W output clock data valid (DAV) polarity
0normal
1inverted
2 to 0 DAVPHASE[2:0] R/W DAV phase select
000 output clock shifted (ahead) by 6/16 t
clk
001 output clock shifted (ahead) by 5/16 t
clk
010 output clock shifted (ahead) by 4/16 t
clk
011 output clock shifted (ahead) by 3/16 t
clk
100 output clock shifted (ahead) by 2/16 t
clk
101 output clock shifted (ahead) by 1/16 t
clk
110 default value as defined in timing section
111 output clock shifted (delayed) by 1/16 t
clk
Table 25. Offset register (address 0013h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 6 - 00 not used
5 to 0 DIG_OFFSET[5:0] R/W digital offset adjustment
011111 +31 LSB
... ...
000000 0
... ...
100000 32 LSB
Table 26. Test pattern register 1 (address 0014h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 3 - 00000 not used
2 to 0 TESTPAT_SEL[2:0] R/W digital test pattern select
000 off
001 mid scale
010 FS
011 +FS
100 toggle ‘1111..1111’/’0000..0000’
101 custom test pattern
110 ‘1010..1010.’
111 ‘010..1010’
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P38

ADC1610S105HN/C1:5

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IC ADC 16BIT PIPELINED 40HVQFN
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