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ADC1610S105HN/C1:5

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P38
ADC1610S_SER 4 © IDT 2012. All rights reserved.
Product data sheet Rev. 04 — 2 July 2012 34 of 38
Integrated Device Technology
ADC1610S series
Single 16-bit ADC; CMOS or LVDS DDR digital output
Table 27. Test pattern register 2 (address 0015h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 0 TESTPAT_USER[15:8] R/W 00000000 custom digital test pattern (bits 13 to 6)
Table 28. Test pattern register 3 (address 0016h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 0 TESTPAT_USER[7:0] R/W 00000000 custom digital test pattern (bits 7 to 0)
Table 29. Fast OTR register (address 0017h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 4 - 0000 not used
3 FASTOTR R/W fast OuT-of-Range (OTR) detection
0 disabled
1 enabled
2 to 0 FASTOTR_DET[2:0] R/W set fast OTR detect level
000 20.56 dB
001 16.12 dB
010 11.02 dB
011 7.82 dB
100 5.49 dB
101 3.66 dB
110 2.14 dB
111 0.86 dB
Table 30. CMOS output register (address 0020h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 4 - 0000 not used
3 to 2 DAV_DRV[1:0] R/W drive strength for DAV CMOS output buffer
00 low
01 medium
10 high
11 very high
1 to 0 DATA_DRV[1:0] R/W drive strength for DATA CMOS output buffer
00 low
01 medium
10 high
11 very high
ADC1610S_SER 4 © IDT 2012. All rights reserved.
Product data sheet Rev. 04 — 2 July 2012 35 of 38
Integrated Device Technology
ADC1610S series
Single 16-bit ADC; CMOS or LVDS DDR digital output
Table 31. LVDS DDR output register 1 (address 0021h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 6 - 00 not used
5 DAVI_x2_EN R/W double LVDS current for DAV LVDS buffer
0 disabled
1 enabled
4 to 3 DAVI[1:0] R/W LVDS current for DAV LVDS buffer
00 3.5 mA
01 4.5 mA
10 1.25 mA
11 2.5 mA
2 DATAI_x2_EN R/W double LVDS current for DATA LVDS buffer
0 disabled
1 enabled
1 to 0 DATAI[1:0] R/W LVDS current for DATA LVDS buffer
00 3.5 mA
01 4.5 mA
10 1.25 mA
11 2.5 mA
Table 32. LVDS DDR output register 2 (address 0022h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 4 - 0000 not used
3 BIT_BYTE_WISE R/W DDR mode for LVDS output
0 bit wise (even data bits output on DAV rising edge/odd
data bits output on DAV falling edge)
1 byte wise (MSB data bits output on DAV rising edge/LSB data
bits output on DAV falling edge)
2 to 0 LVDS_INT_TER[2:0] R/W internal termination for LVDS buffer (DAV and DATA)
000 no internal termination
001 300
010 180
011 110
100 150
101 100
110 81
111 60
ADC1610S_SER 4 © IDT 2012. All rights reserved.
Product data sheet Rev. 04 — 2 July 2012 36 of 38
Integrated Device Technology
ADC1610S series
Single 16-bit ADC; CMOS or LVDS DDR digital output
12. Package outline
Fig 35. Package outline SOT618-1 (HVQFN40)
terminal 1
index area
0.51
A
1
E
h
b
UNIT
ye
0.2
c
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
6.1
5.9
D
h
4.25
3.95
y
1
6.1
5.9
4.25
3.95
e
1
4.5
e
2
4.5
0.30
0.18
0.05
0.00
0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT618-1 MO-220- - - - - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT618-1
HVQFN40: plastic thermal enhanced very thin quad flat package; no leads;
40 terminals; body 6 x 6 x 0.85 mm
A
(1)
max.
A
A
1
c
detail X
y
y
1
C
e
L
E
h
D
h
e
e
1
b
11 20
40
31
30
21
10
1
X
D
E
C
B
A
e
2
01-08-08
02-10-22
terminal 1
index area
1/2 e
1/2 e
AC
C
B
v
M
w
M
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D
(1)
E
(1)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P38

ADC1610S105HN/C1:5

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IC ADC 16BIT PIPELINED 40HVQFN
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