ADC1610S_SER 4 © IDT 2012. All rights reserved.
Product data sheet Rev. 04 — 2 July 2012 13 of 38
Integrated Device Technology
ADC1610S series
Single 16-bit ADC; CMOS or LVDS DDR digital output
10.3 SPI timings
[1] Typical values measured at V
DDA
=3V, V
DDO
=1.8V, T
amb
=25C and C
L
= 5 pF; minimum and maximum
values are across the full temperature range T
amb
= 40 C to +85 C at V
DDA
=3V, V
DDO
=1.8V.
10.4 Typical characteristics
Table 9. SPI timings characteristics
[1]
Symbol Parameter Conditions Min Typ Max Unit
t
w(SCLK)
SCLK pulse width - 40 - ns
t
w(SCLKH)
SCLK HIGH pulse width - 16 - ns
t
w(SCLKL)
SCLK LOW pulse width - 16 - ns
t
su
set-up time data to SCLK HIGH - 5 - ns
CS
to SCLK HIGH - 5 - ns
t
h
hold time data to SCLK HIGH - 2 - ns
CS
to SCLK HIGH - 2 - ns
f
clk(max)
maximum clock frequency - 25 - MHz
Fig 6. SPI timing
t
su
SDIO
SCLK
R/W
W1
W0 A12 A11 D2 D1
D0
t
su
t
h
t
h
t
w(SCLK)
005aaa065
CS
t
w(SCLKL)
t
w(SCLKH)
Fig 7. Capacitance as a function of frequency Fig 8. Resistance as a function of frequency
f (MHz)
50 550450250 350150
001aam619
2.8
2.6
3.0
3.2
C
(pF)
2.4
f (MHz)
50 550450250 350150
001aam614
8
4
12
16
R
(kΩ)
0
